verilog for full_adder

Synthesizable model of Atmel ATmega103 microcontroller. (VHDL IP)-Synthesizable model of Atmel Application of ATmega103 mi crocontroller. (VHDL IP)

计数器的程序，eda编程用的，vhdl语言编程，大家下载看看吧(Program counter, eda programming used, vhdl programming )

7对于进入密码锁的按键，假设复位后七个灯显示" 0"，而使用sw5、sw6 2，则只要按下并松开sw5后七个灯就显示" 5"，而只要按下并松开sw6，七个灯就正确显示值" 6

七段数码管显示数字时 使用VHDL语言编写(VHDL The seven-segment LED display digital clock)

四轴动力模块，用一个顶模块控制，输入有：油门（20档）；指令；水平仪控制指令，4个输出口(Axis power modules, with a top module control inputs are: accelerator (20 files) instruction Level control instructions, four output ports)

说明：  acousting fingerprint enhancement

说明：  经典的雷鸟车灯控制电路设计，各大高校实验必做题目(Thunderbird classic light control circuit design, major colleges and universities must do experimental subjects)

verilog 语言写的FPGA内部实现硬件浮点乘法器的源码，两个时钟周期完成一次浮点乘法运算(The FPGA language written in Verilog implements the source of the hardware floating point multiplier, and completes the floating point multiplication operation in two clock cycles.)

一个有关于UART开发的自己的一个VHDL代码-A UART has developed its own about a VHDL code

串并转换程序，由串行输出转换为4位的并行输出-String and the conversion process, from the serial output is converted to 4-bit parallel output