verilog for full_adder

这是用VHDL编写的译码程序,程序简单易懂-VHDL prepared decoding procedures that are simple to understand

ALTERA FPGA CLPD

基于QuartusII环境下以模块化的形式做成的视频复合同步信号。-QuartusII-based environment to create the form of modular composite video sync signal.

说明：  基于PCF8591数模转换和DDS技术的信号发生器系统设计(Design of Signal Generator System Based on PCF8591 Digital-to-Analog Conversion and DDS Technology)

AD7266的Verilog驱动程序,已仿真通过,可直接在EDK下使用.

用verilog编写的1024点的fft快速傅立叶变换-Verilog prepared using 1024 point fft Fast Fourier Transform

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

OFDM中的IFFF模块实现，基于verilog实现，通过验证(OFDM module in IFFF)

4位电子密码锁，带键盘扫描、按键防抖动、LCD驱动编译码-four electronic password lock with a keyboard scan button shake, LCD driver encryption

第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。(Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.)