FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合...

说明：  一个编码解码系统，其中包含一个信号发生器（用查找表方式实现）、一个m序列生成器（用来编码和解码用）、一个FiFo队列用来做缓存以及用串口方式进行收发读取数据。(An encoding and decoding system, which includes a signal generator (implemented by look-up table), an m-sequence generator (used for encoding and decoding), a FIFO queue for caching, and a serial port for receiving, transmitting and reading data.)

wishbone 源代码，opencore-wishbone source code, opencore

在spartan－3e上利用八个led实现流水灯效果-Spartan-3e in the use of eight led lights to achieve the effect of flowing water

16QAM,64QAM,256QAM调制下的球形译码(16QAM, 64QAM, 256QAM modulation sphere decoding)

说明：  使用DE2实现DDS，步骤简单，配置管脚可自查看(Using DE2 to realize DDS, the steps are simple and the pins can be self-checked.)

6对于进入密码锁的按键，假设复位后七个灯显示" 0"，使用sw1、sw2 2，然后只要按下并松开sw2，七个灯上就显示" 2"，而只要按下并松开sw1，七个灯上就正确显示值" 1

四选一编程语言，可以自动生成四选一器件。-First elected four programming languages, you can automatically generate a four selected devices.

HLD开发语言ADHL介绍。ADHL是ALTERA公司开发的硬件描述语言，也是一种较为流行的开发工具。是介绍AHDL的入门培训资料。-HLD development language ADHL introduction. ADHL is ALTERA developed hardware description language, but also a more popular development tools. AHDL is the introduction of induction training information.

闪耀光栅 有带阻滤波器作用的闪耀光纤光栅，反射角度可以控制(Blazed grating)

《Verilog HDL 程序设计教程》8-"Verilog HDL Design Guide" 8