FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合...

说明：  阿尔泰PCI8664的采集卡labview程序(PCI8664，labview，programm)

verilog实现的简易通用型CPI接口-verilog easy to achieve CPI general-purpose interface

试设计一种彩灯控制器控制8盏灯。该彩灯控制器有4种自动切换的花样。第一种花样为彩灯从右到左，然后从左到右逐次点亮，全灭全亮；第二种花样为彩灯两边同时亮一个逐次向中间移动再散开；第三种花样为彩灯两边同时亮两个逐次向中间移动再散开；第四种花样为彩灯两边同时亮三个，然后四亮四灭，四灭四亮，最后一灭一亮。四个花样自动变换，重复以上过程。输入时钟频率为500Hz，灯亮的时间在1―4秒之间，可以自由控制。电路中以“1”代表灯亮，以“0”代表灯灭。-Lantern try to design a controller to control 8 lights. The controller has four kinds of lanterns automatically switch the pattern. The first lantern pattern for right-to-left, and then lit from left to right each time, the whole body light second pattern for a lantern light at the same time on both sides of successive spread to the middle of moving again third pattern for lantern light at the same time on both sides to the middle of two successive re-dispersed mobile fourth pattern for the lantern light at the same time on both sides of the three, then four out four bright, four out four-liang, the last light out. Automatically transform the four patterns, repeat the process above. Input clock frequency of 500Hz, the time for lights between 1-4 seconds, they can con

VLSI implementation of high speed and high resolution FFT algorithm based on Radix 2 for DSP application

很好的NAND Flash 硬件驱动语言，支持VHDL和verilog 语言方便移植，如果有想用FPGA直接驱动NAND flash而又不知如何下手的朋友肯定喜欢。(NAND Flash Controller Reference This reference design is used to interface a NAND Flash device and provides a simple host end interface. The host end interface of this design is user-configurable. It provides buffer select signal, buffer write enable signal, address bus, data bus, error status signal, control and handshake signals for the user......)

vhdl语言和verilog语言转换工具 能很容易的实现两种语言的相互转换-verilog language vhdl language and conversion tools can easily achieve the conversion between two languages

用VHDL开发的棒球游戏，可以在QuartusII环境下编译，适用于各种FPGA开发板。-VHDL development of the baseball game, in QuartusII environment compiler, apply to all FPGA development board.

本代码主要功能是PPM解码，采用Verilog语言，通过移位寄存器和组合电路实现解码。(The main function of this code is PPM decoding.)

VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是1-20个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC published examples here is 1-20 months

xilinx CTC IPcore(encoder 和 decoder)的测试，经过AWGN信道。 -This simulation uses a AWGN module to include noise as part of the simulation. Prior to running the simulation, the UniSim models for the encoder and decoder must be generated as well as the AWGN module.