FIFO的Verilog程序 已在modelsim中编译通过 并且可以通过DC进行综合...

FPGA测序和DDS产生各种波形程序，用Atral器件开发(FPGA sequencing and DDS generate various waveform programs.)

该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)

说明：  用zynq实现片内的数模转换，基于最新的zynq平台(zynq xadc on FPGA arm)

xilinx Spartan 6 PCIE仿真教程，PIO方式，带有TLP包分析。(XILINX PCIE tutorial device spartan6 PCIE core version V2.4)

LED闪烁的VHDL代码

使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过(Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by)

LAB 9, Excercise for DE2 Altera

可测试74LS00，74LS01，74LS02，74LS03等等芯片的功能是否正常。

verilog例子资源，对于初学者很有帮助。-verilog examples of resources are very useful for beginners.

一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典-Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!