一个4×4矩阵键盘接口程序的Verilog设计（FPGA）

DE2 altera board vhdl design

本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)

FIR filter up to 128x

本例源代码文件由用户按照书中的操作步骤自己生成，“Example-2-1Project_Navigator_Demo源代码”目录下为源代码的参考文件。“Example-2-1Project_Navigator_Democounter”目录下为完整的工程，包括源代码文件、综合与实现的结果文件、ISE工程文件等，可以使用ISE工程管理器打开工程，供读者参考(In this case the source code files by the user in accordance with the steps the book itself is generated, "Example-2-1 Project_Navigator_Demo source" directory as the source code reference document. "Example-2-1 Project_Navigator_Demo counter" directory for a complete project, including source code files, integrated with the realization of the outcome document, ISE project file, etc. You can use ISE Project Manager, open the project for the reader is referred to)

VEROLOG的重要PPT资料,对初学者非常有益处-PPT important VEROLOG information is very useful for beginners

jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)

通过监测工作状态实现带有IIC通讯功能的数据发送接收(to implement the sending and receiving data function of iic communication )

基于研华采集卡的FIFO双缓存区高速数据采集(FIFO DAQ)

这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting

说明：  AD9361资料文档及其寄存器配置参数文档(Ad9361 data and configuration parameter document)