通过VHDL语言的例子，通过乒乓球运动FPGA原型楚原型（1章）

Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

this is bpsk code in matlab

这是用verilog硬件描述语言编的5分频代码-This is verilog hardware description language code is compiled by five divider

matlab dsp building fpga(matlab dsp building )

xilinx 的edk软件的应用软件开发入门 (xilinx edk)

FPGA based design and Implementation of Advanced Encryption Standard

说明：  DDS的基本原理主要由五部分组成，分别是；相位累加器，正弦波形存储器，数模转换器，低通滤波器和时钟，将相位累加器输出的数据作为地址，用来查询表的数据，将取出的正弦数据通过数模转换器输出模拟信号，模拟信号再通过一个低通滤波器输出纯净的正弦波信号。(The basic principle of DDS is mainly composed of five parts: phase accumulator, sinusoidal waveform memory, digital to analog converter, low-pass filter and clock. The output data of phase accumulator is used as address to query the data of table. The extracted sinusoidal data is output analog signal through digital analog converter, and the analog signal is output pure sine through a low-pass filter Wave signal.)

DESCRIPTION OF FULL ADDER

说明：  FPGA核心板EP4CE10F17C8电路原理图(Circuit schematic diagram of EP4CE10F17C8 core board of FPGA)

SPI Verilog code with programmable clock