基于FPGA的电子时钟设计

verilog hdl 编写的64点fft代码，适合很多芯片(coded by verilog hdl that implement 64 point fft, suite to many core)

Spartan® -3E 现场可编程门阵列家族是为满足对成本敏感的消费电子大量应用的需要 而特别设计的。 (Field Programmable Gate Array family needs is to meet the cost-sensitive applications, a large number of consumer electronics Specially designed.)

是用VHDL语言写的对A/D转换模块的控制程序，希望对大家有帮助。-VHDL language is used on the A/D conversion module control procedures, in the hope that everyone has to help.

verilog例子，有130多个，值得参考，新手很有帮助-Verilog example, there are more than 130, it is also useful, very helpful to novice

sub opercore USB CRC5 and CRC16 Modules //// //// //// //// //// //// Author: Rudolf Usselmann //// //// rudi@asics.ws //// //// //// //// //// //// Downloaded from: http://www.opencores.org/cores/usb/(sub opercore USB CRC5 and CRC16 Modules//////////////////////// Author: Rudolf Usselmann//////// rudi@asics.ws//////////////////////// Downloaded from: http://www.opencores.org/cores/usb/)

程序来自《现代通信系统－使用matlab》英文版 已经调通！并加上了注释。 希望对大家有帮助4(fpga)

Verilog语言的流水灯设计程序，对初学者很有用。(Water lights Verilog language design program useful for beginners.)

verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)

资源描述针对于Virtex5FPGA的DDR2读写测试的完整工程,已测试可以使用，可以根据自己的ddr2配置自行更改。。。。

纠错和单故障检测代码使用正交拉丁方是用VHDL语言写的。