通信基带信号发生器的设计，采用单片机输入频率和波形，在FPGA中实现频率和波形生成...

自己根据xapp1052修改的源代码，已经编译成功，并应用在开发板上。(According xapp1052 own modified source code has been successfully compiled and used in the development board.)

synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料(synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials)

将VHDL程序下载到DE2开发板，引脚分配时需要知道的芯片每个引脚功能(VHDL program will be downloaded to the DE2 development board, you need to know when the pin assignments for each pin of the chip functions)

ahb to apb master verification

采用CORDIC算法的直接数字频率合成器的设计(CORDIC algorithm uses direct digital frequency synthesizer design)

掌握SDRAM数据读写、刷新、初始化以及FPGA串口收发时序，熟练FIFO IP核的生成和调用。(Master SDRAM data read and write, refresh, initialization and the timing of sending and receiving of the serial port of the FPGA, skilled in the generation and invocation of the FIFO IP core.)

vhdl的一个串行序列信号发生器的设计与实现-vhdl sequence of a Serial Signal Generator Design and Implementation

Multipleksor 3 to 1 - 3x1bit in, 1x1bit out

本练习的目的是构建和使用计数器。所设计的电路将在计算机上实现

IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY