通信基带信号发生器的设计，采用单片机输入频率和波形，在FPGA中实现频率和波形生成...

Simple vhdl description to show numbers on 7-segment s on Altera DE2 board.

浙江大学体系结构实验课代码 实现5级流水线带有停顿，旁路和控制竞争的处理。(Experimental Architecture, Zhejiang University course code with a pause 5-stage pipeline, bypassing the treatment and control of competition.)

本程序显示在 BCD display 数从 0 到 9999.This 程序进行了智能 2 FPGA 板。

FPGA代码，Designing_with_Quartus_II_Exercises_Ver11_v4_2.doc-FPGA code Designing_with_Quartus_II_Exercises_Ver1 1_v4_2.doc

AD7266的Verilog驱动程序,已仿真通过,可直接在EDK下使用.

几种常用乘法器的Verilog、VHDL代码-Several common multiplier Verilog, VHDL code

eda的入门学习课件，老师不错，内容页挺好的(eda learning files)

this project is about FIR FIlter By VHdl codes in the ISE.

8位并行输入的数转换成串行输出，是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)

fpga平台实现srio通信，以及srio端口寄存器设计。(FPGA platform to achieve sRIO communication, as well as sRIO port register design.)