通信基带信号发生器的设计，采用单片机输入频率和波形，在FPGA中实现频率和波形生成...

hdlc协议的相关程序，用verilog语言编写，供大家交流学习(hdlc protocol procedures using Verilog language for the exchange of learning)

ise平台模拟UART，并与PC机实现收发（+1）(ISE platform simulation UART and transceiver.)

利用Verilog HDL对AD7705进行控制ADC采样，实验室师兄的-Using Verilog HDL to the AD7705 control ADC sampling, laboratory师兄the

基于FPGA的local bus接口。包含基于fifo和普通寄存器的两种方案。(FPGA-based local bus interface. Based fifo contains two programs and the general register.)

ISE时序约束笔记——Global Timing Constraints，这个文档中详细介绍了如何使用ISE中约束工具和原理，对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)

verilog 写的 电话计费器程序-verilog to write a telephone billing program

此压缩包里面有基于vivado平台的工程，包括了正弦信号的产生，还有fir滤波器的设计以及fft算法的设计实现(in this package,there are three projects of the generation of the signal of sin and the design of fir filter and the ari)

文件中包含BFSK、DPSK、BPSK、QPSK等等数字调制程序。(File contains the BFSK, DPSK, BPSK, QPSK, and so on digital modulation process.)

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

基于FPGA的快速傅里叶变换。使用ISE软件以及MATLAB验证。(FFT based on FPGA)