出租车计价器VHDL程序与仿真 的vhdl源代码

一款240＊128的LCD模块在ALTERA　FPGA　NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考-A 240* 128 LCD module in the ALTERA FPGA NIOS application, write your own AVALON Bus IP, including all source code can be easily used in NIOS for reference

注意：是verilog语言写的 一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加(Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder)

本程序是用vhdl开发的实现并串转换功能的程序。(This procedure is developed using VHDL implementation and string conversion function of the program.)

this the for a equiripple filter-this is the for a equiripple filter

涉及到常用的模块，参数可配置，可以很方便的集成到应用中(Related to commonly used modules, parameters can be configured, can be easily integrated into applications)

Material to learn how to use system verilog and how to write testbenches for verification.

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)

SMT32F4 i2s 全双工配置，自己测试OK的，大家可以看看(SMT32F4 i2s 全双工配置)

this file is vhdl code of alu

说明：  matlab code for JTAG cable checking