VHDL语言实现fft滤波算法

入门，verilog语言，实现字符型液晶1602的显示，及按键控制-verilog

说明：  电网协议信道解交织器设计FPGA实现，适用于PB16的宽带电力线载波通信(Grid protocol channel deinterleaver design FPGA implementation, suitable for PB16 broadband power line carrier communication)

说明：  FPGA测试程序，仅供测试硬件是否能够运行，主要功能是点亮运行指示灯(The main function of the test program of FPGA is to light the running indicator.)

The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.

本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)

Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。 模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。 (Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)

Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM

资源描述VGA视频图形阵列（VGA）接口是一三排15针de-15连接器。15针VGA接口是许多视频卡，发现电脑显示器，以及一些高清晰度电视机。在笔记本电脑或其他小型设备，迷你VGA端口有时用于全尺寸的VGA接口的地方。

高速高性能FFT处理器的VLSI实现研究，适合做FPGA的技术人员参考研究FFT-High-speed high-performance FFT processor VLSI realization of research, suitable for FPGA technology reference study FFT

ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules