Cirrus Logic EP9302 原理图 ORCAD格式

基于FPGA与LM4550B的AC97软声卡VHDL语言驱动，版本2.0-FPGA-based soft and LM4550B the AC97 sound card driver VHDL language, version 2.0

基于verilog语言的差分曼彻斯特编码，内包含数据的采集，CRC校验（8位），和编码，输出。附有完整的工程文件。可直接调用modelsim仿真。(Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be called directly.)

dekoder code s Gray to cod „ 1 from 16”. This is program i VHDL

基于单片机的DDS信号发生器，具有DDS思想的单片机编程。。。(Sunplus based DDS signal generator with DDS thinking microcontrollers. . .)

用verilog实现的UDP协议，包括arp，udp，ip分段协议等，对于想用FPGA实现TCP/IP协议的人来说，应该会起到一定的帮助作用(Implemented with verilog UDP protocols, including arp, udp, ip fragmentation protocol, etc., who want to achieve TCP/IP protocol with the FPGA people, should play a helpful role)

FPGA 点亮数码管的灯，本例程支持6位数码管，因为我的FPGA开发板是这样子的(The lamp of digital tube illuminated by FPGA)

在quartus中使用IP核的实际例子与流程-The use of IP in the Quartus practical examples and nuclear flow

IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY

采用vhdl语言实现12路的pwm波控制。-Language implementation using vhdl wave pwm control of the road 12.

Cadence_manual_1.2.pdf