Cirrus Logic EP9302 原理图 ORCAD格式

说明：  altera ram ip教程。对RAM进行读写操作，写32个数据到RAM中，再将写入的32个数据从RAM中读出。(altera ram ip.write data to ram and read the data from the ram.)

vhdl very good debug release vhdl very good debug release

基于FPGA的Verilog语言的智能小车，已经经过测试。(FPGA-based smart car Verilog language, and has been tested.)

UART文件 包括发送器 接收器 fifo 测试文件(UART file includes a receiver transmitter fifo test files)

32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add

三层电梯的详细电路 Foundation版 包括强行开关门打断(Elevator control Foundation project)

基于PCI总线和LPC接口的POST主板诊断卡代码，已经通过fpga测试可以使用，性能非常稳定。(Based on the PCI bus and LPC POST motherboard diagnostic card code to interface fpga has passed the test can be used, the performance is very stable.)

Viterberi 解码器使用 vhdl 编程实现将被用于制作增强功能

说明：  FPGA与PC端实现串口数据的收发，先从PC端接收数据，然后发回给电脑，可通过串口助手验证。(The serial port data is sent and received between the FPGA and the PC. First, the data is received from the PC, and then sent back to the computer. It can be verified by the serial port assistant.)

dsp与fpga通信的verilog程序，强烈推荐欢迎参考(dsp and fpga verilog communication program, it is strongly recommended to welcome reference)