FPGA60进制数码管显示VHDL代码

低频数字式相位测量仪，数码管显示相位差，精度为0.1(Low frequency digital phase measuring instrument, digital pipe display phase difference )

使用verilog语言描述的二阶巴特沃斯IIR滤波器，程序中有参数说明，已经运行通过(Using verilog language to describe the second-order Butterworth IIR filter, the program has parameter description has been run through)

papers based on distributed arithmetic.

实现psk调制解调，vhdl代码，仿真文件也有(psk shixian tiaozhiyujietiao)

图像降噪GUI界面，用到butterworth滤波器，中值滤波器和维纳滤波器，仅供参考。(noise reduction using media filter )

用verilog写的基于cpld的出租车计费器的源码，需要的参考一下-Use verilog to write a taxi based cpld billing device source code, need to refer to

Very suitable for the study using computer vision, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. The performance of the program has reached a high level.

本例是一个6层电梯的控制系统,VHDL原程序,状态机,控制器-This case is a 6-storey elevator control system, VHDL original procedures, state machine, controller

实现任意倍数的倍频,帮助大家解决VHDL倍频问题,(The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,)

E1 deframmer and Frammer.