Interface design between microprocessor and cpld ,suit for IC design and applica...

本程序主要是实现xinlinx fpga与dsp之间的双工通信(This program is to achieve duplex communication between xilinx fpga and dsp)

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

基于FPGA的VGA驱动代码VHDL 在显示屏显示一个汉字-FPGA-based VHDL code of the VGA driver that a character in the display

Quartus II 7.2最完美的license破解器!(Quartus II 7.2 FULL and perfect License!)

用vhdl设计实现的多功能电子钟，可有日历，闹钟，修改等多种功能-With VHDL Design and Implementation of the multi-functional electronic bell, can have a calendar, alarm clock, to amend a variety of functions such as

16位右移位寄存器 下面描述的是一个位宽为16位的右移位寄存器，实际具有环形移位的功能，是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时，输入信号的最低位移位到最高位，其余各位依次向右移动一位。(16-bit right shift register The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)

说明：  假设每个从设备中有可访问APB寄存器16个，位宽均为32比特，16个寄存器的访问地址计算方式为 基址 +　寄存器编号左移２位（byte 偏移）(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)

本例程位于 VMD642_CPLD目录中。 使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使 用 Verilog HDL书写，编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)

AUDIO音频模块AN831的录音及播放FPGA代码，测试通过(AUDIO audio module AN831 recording and playback of FPGA code, the test passed)

说明：  misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)