Interface design between microprocessor and cpld ,suit for IC design and applica...

电梯控制 记忆，上升下降停站 超载报警故障.....。-Verilog EDA dianti

采用Verilog HDL硬件语言设计,实现基本的公用电话计费功能,设计完整.-Using Verilog HDL language hardware design, the realization of the basic public telephone billing function, design integrity.

vivado lwip 应用文档 基于zynq 7020(vivado lwip example text of zynq)

基于FPGA 的12864液晶显示汉字，用verilog编写的。(12864 liquid crystal display Chinese characters based on FPGA, written in verilog.)

温湿度传感器sht30驱动，系统时钟为125M可读出温湿度。(sht30 driver,sysclk=125MHZ)

RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块(RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module)

通过VHDL语言进行数字信号处理的FIR操作，可以很好的实现滤波功能，有很好的作用，-Through VHDL languages digital signal processing FIR operation, can good realization filtering, have good role

正弦信号发生器（可扫频）通过验证 正弦信号发生器-Sinusoidal signal generator (which can be swept) through the validation of sinusoidal signal generator

最新的CCSDS高光谱图像压缩算法标准的FPGA实现，用VHDL实现的。可参考。绝对物有所值，希望对你的设计有所帮助!

自己写的扩展功能时钟，增加了年、月日计时，verilog代码，已在spatarn3实现。-Write their own extensions clock, an increase of the year, month day time, verilog code in spatarn3 realize.