MS5611控制 温度 压力 fpga vhdl

《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)

Multi-Digital Down Converter design.

ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口(ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface )

一个用verilog实现的五子棋程序，用在fpga上，连接显示器，可选择与电脑对战或是双人对战，按wsad控制方向，回车控制落子，程序会自动判断输赢并显示结果(A 331 procedures implemented by verilog, used in fpga, connect the monitor, you can choose to play against the computer or a double play, press wsad control the direction, carriage control Lazi, the program will automatically determine the winners and losers and display the results)

原创。掷骰子游戏，VHDL，quartus，北京邮电大学数电实验，实现随机掷骰子游戏，在数码管显示点数，点阵显示输赢，有开机动画以及开机音乐，可实现多人游戏等(games, VHDL, quartus,experiments of BUPT, pure originality,random game, in the digital display dots, dot matrix display winning or losing, there are boot animation and boot music, multiplayer gaming can be achieved)

FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。(FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.)

任意数据发生器的源代码-arbitrary data source code generator

mimo—ofdm线性卷积，实现输入的800位宽的数据同两个序列的卷积(Mimo- ofdm linear convolution 800 bits wide input data with the convolution of two sequences )

实现十六位加法器，是书籍上配套的应该可用-This is an 16 bit adder using vhdl

使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。-use of the VHDL language ALTERA company"s board up3 have vga signal containing a detailed analysis and explanation is a good guide.