Embedded System multiplier test report including source code language used VHDl

BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

该源码可基于FPGA设置多分辨率的HDMI显示，且其包含了完整的时序和端口、地址映射，可以很方便的将其移植(The source code can be set based on FPGA multi-resolution HDMI display, and it includes a complete timing and port, address mapping, it can be easily transplanted)

100个VHDL的例子-100 examples of VHDL

说明：  浮点数加法器的源代码,实现浮点数的加法功能，浮点数遵循的是IEEE745标准(floating_piont addition)

浙江大学体系结构实验课代码，5级流水线实现旁路和停顿(5-stage pipeline to achieve realization of the bypass pipeline bypass pause 5 pause)

基于FPGA的抢答器程序，VHDL 语言描述。(FPGA)

VHDL Vendingmachine source

RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference

非常详细的千兆以太网MAC verilog代码，可以供硬件设计时有关网络的开发参考(Very detailed Gigabit Ethernet MAC verilog code, can be used for hardware design of the network to develop a reference)

十进制计算机，实现十进制计数功能，简单可靠(vhdl)