8路视频光端机的VHDL源码，此硬件使用以太网的SERDES 借用TBI接口传输PCM视频信号。...

FPGA代码，包含地址译码模块、16位锁存器、AD片选、死区及滤除窄脉冲、过流和短路保护、解除脉冲封锁模块、PWM模块、PWM选择 (FPGA code, including the address decoder module 16 latches, AD chip select, filter out the dead and narrow pulse, overcurrent and short circuit protection, lifting the blockade pulse module, PWM module, PWM selection)

Simulating the functions of POC.(Simulating the functions of POC. In VHDL, with ISE.)

本程序是在AWGN下的LDPC码的仿真程序，本程序优点是译码效率高，速率很快，可以仿帧数很大的图。(the decoder for LDPC under the AWGN channel)

LVDS并行数据传输，来自XILINX官网(LVDS Parallel Data Transfer)

CS5460校准程序，控制器为C8051F310，SPI通信协议，可以作为电表芯片示例(CS5460 calibration procedure, the controller for the C8051F310, SPI communication protocol, as the meter chip sample)

Quartus II 7.2最完美的license破解器!(Quartus II 7.2 FULL and perfect License!)

fft快速傅立叶变换源码-the source of fast fft transform

说明：  KMP算法的Verilog HDL实现，模式串从模块的外部输入，计算next函数，然后进行KMP匹配。有仿真。环境为Quartus II 8.0 Web Edition。(Verilog HDL implementation KMP algorithm, pattern string from the module' s external input, calculate next function, then KMP matching. A simulation. Environment for the Quartus II 8.0 Web Edition.)

FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序(FPGA and DSP EMIF communication)

FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序(FPGA and DSP EMIF communication)