这是我自己写的两个8位二进制数的乘法程序，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！...

自己编写的同步和异步FIFO的verilog代码，验证过，有可靠性(Verilog code of my own synchronous and asynchronous FIFO, verified,and reliable.)

信号源模块源程序,可以实现程序模块的实现，然后发生需要的程序(Source module source code, you can achieve the realization of the program modules, and the occurrence of the required procedures)

简要地说明时序约束的内容，对入门级的朋友相当起到引导的作用(Briefly describes the content of timing constraints on entry-level friends rather play a guiding role)

VHDL语言，设计一个在DE2平台的8个七段数码管上循环显示HELL0的程序，采用按键控制循环的速度，慢速循环时间间隔为1S，快速循环时间间隔为200ms。(VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fast cycle time interval is 200ms.)

用FPGA实现 VGA显示的图像显示控制器设计 用VHDL实现 硬件实现是屏幕上面出现彩色条纹(VGA display with FPGA image display controller design Using VHDL hardware implementation is colored stripes appear above the screen)

本文通过大量的例子讲解VHDL。对于初学者来说是一本非常好的 教材-Based on the large number of examples of VHDL. For a newcomer it is a very good teaching

FPGA核心板EP4CE10F17C8电路原理图(Circuit schematic diagram of EP4CE10F17C8 core board of FPGA)

Verilog 编写的串口通信模块 带测试代码(Verilog prepared by the serial communication module with a test code)

单片机与FPGA串行通信的源代码，非常实用哦-Single-chip serial communication with the FPGA source code, very useful Oh

关于VHDL和verilog的数码管显示程序，写的很好，值得参考。(About VHDL and verilog digital tube display program, write well, worth considering.)