sram 读写小程序，用verilog编写的，请各位高手指教

关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)

libero soc工程，实现通过串口接收到单字节数据后并返回发送给上位机(Libero SOC project, which realizes receiving single byte data through serial port and sending it back to host computer)

我们使用此代码开发 plc 在 fpga 硬件计数器的程序

FPGA的存储器代码的VHDL,verilog描述及测试代码-FPGA memory code VHDL, verilog description and test code

msttr是用vhdl语言开发的一个交通灯程序-msttr VHDL language is a development of the traffic lights procedures

此练习的目的是要了解如何连接简单的输入和输出到 FPGA 芯片的设备和 实现电路，使用这些设备。我们将作为投入 DE2 系列主板上使用 SW17

摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。 关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)

10对于进入密码锁的按键，假设复位后七个灯显示0，使用sw1、sw2两个键输入，只要按sw1键，并使七个灯显示每秒速度加1的值，但释放sw1键后停止。

乘法器功能 直接实现两个数字信号的相乘～-Multiplier features two digital signal direct implementation of the multiplication ~

使用FPGA测量频率大小，并且在数码管上进行显示(Frequency measurement using FPGA and display on digital tube)