蓝牙HCI―UART与并口的FPGA控制接口设计

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

AB相编码器解码接口_PWM输出SOPC方案及其在运动控制卡和伺服驱动器中的应用(AB phase encoder decoder interface _PWM output SOPC program and its application in motion control card and servo drive)

fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim

串口通信通用模块，FPGA Verilog语言 ise，vivado环境(uart,FPGA Verilog, ise,vivado)

altera公司cpld/fpga开发软件quartus2中文使用教程-altera company cpld/fpga development of software to use Chinese quartus2 Guide

时钟分频代码，PWM产生 RTL 源代码。(clock divider，PWM generator RTL Source Code)

this contain the source code for noise cancellation ,which can be used in c platform.

说明：  Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)

SDRAM的vegilog代码，做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM