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StopWatch
This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
- 2013-10-04 00:53:49下载
- 积分:1
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application-in-card-and-servo-drive
AB相编码器解码接口_PWM输出SOPC方案及其在运动控制卡和伺服驱动器中的应用(AB phase encoder decoder interface _PWM output SOPC program and its application in motion control card and servo drive)
- 2012-03-22 12:44:52下载
- 积分:1
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fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过...
fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
- 2023-07-19 00:45:03下载
- 积分:1
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uart
串口通信通用模块,FPGA Verilog语言 ise,vivado环境(uart,FPGA Verilog, ise,vivado)
- 2020-06-22 07:20:01下载
- 积分:1
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altera公司cpld/fpga开发软件quartus2中文使用教程
altera公司cpld/fpga开发软件quartus2中文使用教程-altera company cpld/fpga development of software to use Chinese quartus2 Guide
- 2022-11-23 18:50:03下载
- 积分:1
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clk_generator
时钟分频代码,PWM产生 RTL 源代码。(clock divider,PWM generator RTL Source Code)
- 2013-08-18 09:29:42下载
- 积分:1
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Noise-cancellation
this contain the source code for noise cancellation ,which can be used in c platform.
- 2012-10-21 23:32:37下载
- 积分:1
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uart-for-fpga
说明: Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA.
Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!
The UART controller was simulated and tested in hardware.
- 2020-06-24 22:00:02下载
- 积分:1
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verilog
关于USB开发的verilog开发程序,非常的全面,学习FPGA开发时用得着。(About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.)
- 2013-12-26 18:29:35下载
- 积分:1
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SDRAM的vegilog代码,做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块...
SDRAM的vegilog代码,做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
- 2022-10-13 14:20:04下载
- 积分:1