蓝牙HCI―UART与并口的FPGA控制接口设计

在altera公司FPGA上自己构建了一个最简单的niosii sopc系统(Altera FPGA company on its own to build a simple system niosii sopc)

该模块已经成功运用在xilinx xc6slx45t，xc6slx75t多个产品中，经过实践证明，采用dna及其加密算法加密是一种成本低廉（无需另外加密芯片）可靠的加密手段。Xilinx Spartan-6 FPGA读取DNA数据并进行比较，产生比较结果信号输出。附带有xilinx DNA.ppt说明及调试注意事项。(The module has been successfully used in xilinx xc6slx45t, multiple xc6slx75t products, proven, and the encryption algorithm uses dna is a low-cost (no additional encryption chip) reliable means of encryption. Xilinx Spartan-6 FPGA reads the data and compare DNA to produce a comparison result signal output. Xilinx DNA.ppt comes with instructions and commissioning notes.)

verilog coding for butterworth filter with cut off frequency with 500hz

数字密码锁的vhdl实现，包括设置密码，修改密码，报警。

说明：  数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)

VC++6.0软件生成Altera公司FPGA内部存储器ROM初始化数据mif格式文件。方便通过QuartusII导入波形等参数。强调这个是例子，生成的是一个定点的正弦数据表文件，需要用到的请自行修改源代码。(This software generates internal memory ROM initialization mif format data file for FPGA product by Altera. Facilitate the passage of the waveform parameters such as import QuartusII)

ep2c5 实现 逻辑门 verilog语言，quartus 2 仿真-ep2c5 the realization of logic gates verilog language, quartus 2 Simulation

mc8051代码，里面功能齐全，调试方便(mc8051 code, inside a full-featured, easy debugging)

combinational circuits code in vhdl

GAL16V8反汇编源程序JED2ABEL.C 把jec汇编成abel文件-GAL16V8 disassemble source JED2ABEL.C the JEC document compiled abel