蓝牙HCI―UART与并口的FPGA控制接口设计

并口通讯代码 并口通讯代码（调试通过） --该代码目前能实现单个字节的收发-Parallel communications code (debugging through)-- The code can now achieve a single byte of Transceivers

vhdl描述的显示代码 maxplus2开发环境-VHDL description of the display code development environment maxplus2

生成一个M伪随机序列码，在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)

基于DE2_70平台，编写nios软核c代码，控制流水灯，硬件实现验证通过，适合入门(Based DE2_70 platform, written nios soft core c code, control water lights, verified by hardware implementation, suitable for entry)

Quartus2环境下基于VHDL状态机的交通灯程序(VHDL state machine traffic lights based on Quartus2 environment)

ram 64KB designed by haneesh in verilog

cycloneII Quartus verilog开发的简单时序电路-cycloneII Quartus verilog to develop a simple sequential circuit

MBD-FPGA数字滤波器设计基本流程,基于DSP builder(MBD-FPGA basic process of digital filter design)

说明：  AD9250是一款双通道14位ADC，最高采样速率250 MSPS，JESD204B Subclass 0或Subclass 1编码串行数字输出(The ad9250 is a dual channel 14 bit ADC with a maximum sampling rate of 250 MSPs and jesd204b sub class 0 or sub class 1 coded serial digital output)

基于tus5000评估板的VHDL源代码，用于超声波检测，xinlinx提供的(Based on the VHDL source code tus5000 uation board, used in ultrasonic testing, xinlinx provide)