ALTERA上DE2平台，利用内部50M Hz时钟，在数码管模拟显示时间(时分秒)。

用verilog编写的包含有与DSP通信，三电平svpwm实现的程序，(Written in verilog contains communicate with the DSP, three-level svpwm realize the procedures)

如果不考虑占空比，直接利用计数器来进行分频，则占空比会发生变化。下面程序实现1：1的三分频。-if not duty cycle directly counter to the use of sub-frequency, duty cycle will change. Below a program : a third of the frequency.

AHB 总线slave verilog实现(Implementation of AHB bus)

光栅尺的四细分和辩向电路，并具有计数器功能，利用Quartus综合，可以参考-Grating four segments and the dialectic to the circuit, and have counter functions, using Quartus integrated, can refer to

可以实现DDS 的正负线性扫频以及在线参数设置(DDS ad9914/ad9915 code)

acousting fingerprint enhancement

一款非常实用的8051IPcore,本人现在做soc的控制部分就是它。(A very useful 8051IPcore, I now control part of the soc is doing it.)

说明：  适合入门及进阶的100个VHDL练习题，从易到难(100 VHDL exercises for beginners and advanced students, from easy to difficult)

A simple Manchester Encoder to convert serial data to Manchester encoded data.