ALTERA上DE2平台，利用内部50M Hz时钟，在数码管模拟显示时间(时分秒)。

Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel.

适用于FPGA的SOPC方面的元器件添加，如COMPNENT-Applicable to FPGA-SOPC area to add components, such as COMPNENT

本代码实现了 ； ；CORDIC  ； 算法语言；

实现任意倍数的倍频,帮助大家解决VHDL倍频问题,(The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,)

Actel双端口存储；通过串口发送数据初始化RAM，然后通过串口返回到上位机的串口调试程序显示(通过串口发送数据初始化RAM，然后通过串口返回到上位机的串口调试程序显示)

that file is different I2S example

四人抢答器，已通过编译，仿真，包括抢答识别、计分、计时、数字显示等功能。-Four Responder, has passed the compilation, simulation, including the answer in his identification, scoring, timing and digital display.

231卷积码的verilog实现，前面是详细的文档说明，有源程序，绝对原创！！！！(Verilog achieve 231 convolutional code, preceded by a detailed description of the document, the source, the absolute originality! ! ! !)

8位相等比较器，比较8位数是否相等 -- 8-bit Identity Comparator -- uses 1993 std VHDL -- download from www.pld.com.cn & www.fpga.com.cn-eight other phase comparators, Comparing the same whether the median 8-- 8-bit Identity Comparator-- uses 1993 std VHDL-- download from www.pld.com.cn

Simulation and Synthesis Techniques for Asynchronous FIFO Design