EP2C35开发板官方原理图,是altera的官方资料。是fpga电路设计的很好参考典范。...

彩灯控制器 vhdl语言开发 eda实验-Lantern controller vhdl language test eda

基于脉动结构的有限域乘法器，verilog代码(Based on the pulse of the structure of finite field multipliers, verilog code)

串行流水线格式:使用COrdic 算法计算反正切:向量模式下求角度 16bit :数据全部补码格式 (Serial line format: Use COrdic algorithm arctangent: seeking angle vector mode 16bit: full complement data format)

Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a classified as low-key is pressed, stop the scan and to maintain the current line-line state, and then read out line state to get the current keys key codes to wait for key pop-up: To detect the lines at all out into a high level after the re-start the scanning process, waiting for the next key.

电子琴程序设计与仿真的vhdl实现的源代码-Electronic organ program design implementation and simulation of vhdl source code

华为内部资料，包括verilog电路设计，硬件工程师手册，verilog约束，synplify使用指南等。内容较全面。(Huawei internal information, including verilog circuit design, hardware engineers manual, verilog constraints, synplify use guides. Content more comprehensive.)

CSC RGB2YUV Verilog source code

说明：  利用vhdl语言编写的译码器程序，采用两种不同方式(The use of language decoder vhdl program, using two different ways)

This is a running 10 bit led on VHDL code including switch to shift from increasing or decreasing

说明：  载波同步是QPSK信号相干解调的一项关键技术。(Carrier synchronization signal coherent QPSK demodulation is a key technology.)