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USB转RS232
USB转RS232RSTTLRS485FT232+SP213串口的原理图AD画的(USB to RS232RSTTLRS485FT232+SP213 serial port schematic AD drawing)
- 2020-07-01 04:20:02下载
- 积分:1
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altera several new FPGA configuration methods and the use of experience
altera的几种新型的FPGA的配置方法和使用心得-altera several new FPGA configuration methods and the use of experience
- 2022-05-09 07:27:04下载
- 积分:1
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SHIFT_8REG是8位的一个具有移位功能的寄存器,每一次数据打入都会从这个寄存器的最低位打入,并相应进行向左移位。
ODD_110BREG是一个3位的备...
SHIFT_8REG是8位的一个具有移位功能的寄存器,每一次数据打入都会从这个寄存器的最低位打入,并相应进行向左移位。
ODD_110BREG是一个3位的备份寄存器,寄存器中存放的是奇数帧的同步头,也就是110。
EVEN_9BHREG是一个8位的备份寄存器,寄存器中存放的是偶数帧的同步头,也就是10011011。这两个寄存器的初始值在系统一开始就打入。
-SHIFT_8REG is eight with a displacement of the functional Register, Each will enter the data from the register into the lowest point, and the left shift accordingly. ODD_110BREG is a three backup Register, the Register is stored in the odd frame synchronization head, is 110. EVEN_9BHREG 8 is a backup Register, which register is kept even the first frame synchronization, is 10011011. This register the two initial value of the system into a start.
- 2022-05-15 03:11:22下载
- 积分:1
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sin_10k
基于FPGA的利用rom进行查询的方式生成一个频率为10KHZ的sin信号,编译成功,并实现功能仿真。(Query based on the the FPGA use of rom generate a frequency of 10 kHz sin signal, compiled successfully and to achieve functional simulation.)
- 2013-04-23 10:47:17下载
- 积分:1
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liushuxian
中文版DLX流水线技术相关方面介绍以及简单应用
适用于面对初学者讲解(Chinese version of the DLX pipeline technology-related aspects of introduction and a simple application
Suitable for beginners to explain face)
- 2014-12-09 21:33:45下载
- 积分:1
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RISC
32 bit RISC Processor with 3 stage pipeline
- 2010-03-03 00:09:16下载
- 积分:1
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a program which divides the clock by 3
a program which divides the clock by 3
- 2022-01-25 14:21:33下载
- 积分:1
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VHDL
先设计序列发生器产生序列:1011010001101010;再设计序列检测器,检测序列发生器产生序列,若检测到信号与预置待测信号相同,则输出“1”,否则输出“0”,并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)
- 2015-01-04 12:35:54下载
- 积分:1
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VHDL 加法器
这个程序是 用于两个浮点数字加法器使用 VHDL 语言。
- 2022-02-06 15:47:18下载
- 积分:1
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FPGA simulation examples, Verilog coding, the process in detail, code easy to un...
FPGA的仿真实例,Verilog代码编写,过程详尽,代码易懂。第二个文档-FPGA simulation examples, Verilog coding, the process in detail, code easy to understand. The second document
- 2022-05-04 23:56:16下载
- 积分:1