非常好的SDRAM Controller 设计文档。工程必备

VHDL cyclic redundancy check generator und receiver

This is counter with T_FF.

将Verilog代码转换成C++代码的软件，C源代码。-soft for changing Verilog code to c++ code ,c code

用VHDL语言实现QPSK调制功能和解调功能,(Using VHDL language features QPSK modulation and demodulation functions,)

说明：  用verilog HDL编程实现的基于DAC0832的三角波信号，可借鉴编程实现DAC0832芯片控制(Programming with verilog HDL DAC0832-based triangular wave signal, we may learn programming DAC0832 chip control)

基本功能的cpu，自定义内存内容~了解CPU运作原理~(design of cpu,VHDL environment~)

用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.

说明：  从github下载的，能够参考设计AXI4的协议接口(AXI4 Verilog template)

4、各个功能的主要源程序 1、移相模块： = 1 * GB2 * MERGEFORMAT ⑴、相位累加器： architecture one of add32 is begin   s

one of example about hardware design language