非常好的SDRAM Controller 设计文档。工程必备

说明：  quartusII 9.1，位同步提取电路，可以实现位同步时钟提取，其中包括分频器，和由D触发器以及与门组成的鉴相器模块。(Quartus II 9.1, bit synchronous extraction circuit, can realize bit synchronous clock extraction, including frequency divider, phase discriminator module composed of D trigger and and gate.)

combinatorial modules

Lab view using FPGA traing on lcd pannel

基于FPGA的神经网络硬件实现中的关键问题研究，适合用fpga研究神经网络的工程人员参考-FPGA-based hardware implementation of neural networks in the study of key issues for research with neural networks fpga reference works

研究信道噪声对M-ary QAM的影响，适合数字通讯从业者(Effect of channel noise on M-ary QAM in)

实现了QPSK的调制，使用了ise自带的dds的IP核(QPSK is modulated and the IP core of DDS is used in ise.)

1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core manual 7.2 5.verilog to achieve serial transmission)

用VHDL语言仿真交通灯 用VHDL语言仿真交通灯-Simulation using VHDL language VHDL language with traffic lights traffic lights Simulation

USB接口控制器参考设计，xilinx提供的VHDL源代码-USB interface controller reference design for Xilinx VHDL source code

here is realized simple FIFO stack in vhdl. very simple example, but very helpful.