Describes how to use VHDL language processor spi interface

quartus环境下开发的三人表决器（三种不同的描述方式）maxplusII兼容

通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)

encoding and decoding of audio signal

ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口(ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface )

clock for spartan 3 evaluatoin board

本压缩包，包换一个用verilog语言实现的huffman编码源程序，同时给出了众多论文和基础知识的文档资料，一应俱全。(The compression package, shifting one using huffman coding verilog language source code, and gives basic knowledge of many papers and documentation, everything.)

it is a matrix library. it is needed for fir fier.

VGA显示控制：时序控制+像素点的颜色处理显示十字光标（vorilog）(VGA Display Control: Timing Control+ pixel color processing and display cross cursor (vorilog))

verilog分频器代码 分为偶数倍分频和奇数倍分频两个verilog源文件 附带一个说明文档-divider verilog code for multiple sub-divided into even and odd frequency divider several times with a two verilog source files documentation

这个课程设计的题目是模拟电压采集电路路与程序设计,报告书的内容都比较详细. (The topics of this course design is an analog voltage acquisition circuit Road and program design, the contents of the report are more detailed.)