基于EDA技术的数字密码锁源程序代码,大学实训用的着

用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE

浮点数运算的FPGA实现，包括仿真文件。-FPGA realization of floating-point operations, including the simulation file

自己编的VHDL的波形发生器 做信号的可以-BOXING

Altera DE2 开发板试验2 第1部分VHDL答案(Altera DE2 Lab2 part1 VHDL answer)

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

verilog 写的工程，是个基于流水线的乘法器(verilog write the works, is based on a pipelined multiplier)

altera的几种新型的FPGA的配置方法和使用心得-altera several new FPGA configuration methods and the use of experience

远立科技FPGA培训文档,关于GFP项目的一些细节，很好的！(Yuan established FPGA technology training documentation)

在quartus平台下使用verilog语言编程实现简单的单流水线CPU，可以执行16条基本指令(Quartus platform in the verilog language programming using a simple single-line CPU, can perform 16 basic instructions)

16QAM调制解调程序画出时域波形、 正交分量、同相分量波形，眼图，散点图等(16QAM modulation and demodulation process to draw time-domain waveform, quadrature components, in-phase component waveforms, eye diagrams, scatter plots, etc.)