quartus环境下开发的三人表决器（三种不同的描述方式）maxplusII兼容...

本例为DAC0832接口电路VHDL原代码-The DAC0832 Interface Circuit Example for VHDL source code

在Xilinx开发环境ISE13.2上用MIG产生的DDR3 SDRAM控制器，里面生成了Core，可用于DDR3读写控制(On the Xilinx development environment ISE13.2 generated with MIG DDR3 SDRAM controller, which generates the Core, DDR3 can be used to read and write control)

说明：  RISC 5级流水线CPU，带HAZARD处理(RISC 5 pipeline CPU with HAZARD processing)

A program for a simple decoder using ModelSim6

this a example for the LCD for altera FPGA cyclone ii EP2C8. implemented in verilog. tested using altera EP2C8 fpga

使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮(A full adder design)

共两个文件，一个是对网络芯片W5500进行控制的master spi接口，另一个是w5500命令控制逻辑，命令格式按照w5500芯片的要求，分为地址段，控制段和数据段进行统一控制。此外提供w5500芯片初始化及读写控制流程图。(A total of two documents, one is the master SPI interface for network control chip W5500, the other is a w5500 command control logic, command format in accordance with the requirement of w5500 chip, divided into address segment, unified control and data segments. In addition to provide w5500 chip initialization and read and write control flow chart.)

串uart的vhdl，verilog，lattic实现原码 里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar

通信基带信号发生器的设计，采用单片机输入频率和波形，在FPGA中实现频率和波形生成-Communications base-band signal generator design, the use of single-chip input frequency and waveform, in the FPGA to achieve the frequency and waveform generation

ALTERA Cyclone1C20 Nios开发板，protel99格式-ALTERA Cyclone1C20 Nios，protel99