此为多功能数字电子钟的vhdl代码，有闹钟、时间可调、计时等功能...

vhdl交通灯实验报告-VHDL traffic lights Experimental Report

用FPGA verilog hdl实现千兆以太网MAC。-Using FPGA verilog hdl realize Gigabit Ethernet MAC.

初学学习verilog的经验，可以帮助新手以正确的思维方式，学习方法学习。(Verilog learning experience)

用VHDL语言编写的LDPC码硬件实现语言，相对于verilog的，比较简单-Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple

BT656 时序, 逐行, 分辨率1280*960@25Hz(BT656 time series, row by row, resolution 1280*960@25Hz)

8b10b编码方式，verilog语言实现，有测试程序。能成功编码。没有环回验证，读者可自行编写环回验证测试程序。(8b10b encoding, verilog language, test procedures. Successful encoding. No loopback verification, readers can write your own loopback verification test procedures.)

说明：  ip core of the transceiver gtx

vga很好的学习材料，测试程序，欢迎下载(vga good learning materials, testing procedures, please download)

verilog语言编写的jtag（边界扫描模块），初学的时候可以看看(verilog language jtag (boundary scan module), a novice when you can look)

vhdl code for obtaining video output through vga port