SDRAM控制器源码，内含完整的控制器verilog源代码和测试代码，超值哈。...

说明：  VIVADO HLS IMAGE 使用文档(vivado image processing example text of zynq)

vga接口的工程实现，基于altera环境，需要的可以-vga interface engineering implementation, based on altera environment, need to take a look at

wavelet transform of a signal,it is important and useful code to trans form frequency to time domain

串并转换程序，由串行输出转换为4位的并行输出-String and the conversion process, from the serial output is converted to 4-bit parallel output

本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA" s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of taking the site to achieve a continuous output waveform.

rebuild file in check for

LDPC码不同码长对比。码率选择1/2.码长分别为256，512，1024.(LDPC codes of different code length contrast. Bitrate select 1/2 yards long were 256,512,1024.)

关于Digilent Atlys Spartan-6 FPGA development board　audio ac97的讲解及具体应用的源码(Digilent Atlys Spartan-6 FPGA development board audio of ac97' s presentation as well as the specific application' s source code)

DDR SDRAM控制器verilog代码及中文说明文档(DDR SDRAM Controller Using Virtex-5 FPGA Devices)

卷积码编码译码程序以及其modelsim仿真波形文件等(Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file)