Fpga开发应用，jtag方面的源代码，VHDL

this is the multiplier 3 module for the reed solomon encoder

Altera DE2 上使用 vhdl 语言设计 RS232 控制器。这是一个串口模块可用于嵌入系统。

计算机中每一条机器指令的执行，都离不开程序计数器的正确执行，本程序实现程序计数器。(Computer implementation of each machine instruction, are inseparable from the correct implementation of the program counter, this program achieve the program counter.)

This tutorial introduce VHDL code for clock pulse and 4-bit counter. With four bits, the counter count from 0 to 15. The timing of the counter is controlled by a clock signal. There will be a clear signal which can reset the counter value.

七段数码管显示的时钟程序VHDL代码 ISE编译环境(SEVEN seg VHDL ISE CLOCK)

MIG IP控制DDR3读写测试，于MIG IP核用户接口时序较复杂，这里给出扩展接口模块用于进一步简化接口时序。(MIG IP controls DDR3 reading and writing tests, and the time sequence of MIG IP kernel user interface is more complex.)

AHB BUS, Master Slave Arbiter -- example(AHB BUS, Master Slave Arbiter)

一第二个计时器为斯巴达 6 fpga-结构设计的

在quartus平台下，并使用verillog hdl编写的时钟分频仿真(In quartus platform and use verillog hdl write clock divider simulation)

说明：  基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。 FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board. FPGA edge detection)