Flash接口控制器的VHDL和Verilog源代码和程序测试

实现在屏幕上显示绿色和红色相间的水平条纹。其中，vga_640x480模块将产生行同步信号hsyn和场同步信号 vsync; vga_stripes模块将产生red、green和blue三个输出。(The horizontal stripes of green and red are displayed on the screen. Among them, vga_640x480 module will produce line synchronization signal Hsyn and field synchronization signal vsync; vga_stripes module will produce red, green and blue three outputs.)

Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.

LCD 驱动的IPCORE，可用于alteraFPGA(LCD driver IPCORE, can be used to alteraFPGA)

verilog 232串口收发程序 在开发板上测试成功过-verilog 232 serial port transceiver program already had some success in the development of on-board test ^ ^

基于芯片MAX502的十二位并行DAC芯片的程序，利用FPGA中的ROM查表进行数据存储-Based on 12 of the MAX502 chip DAC chips in parallel procedures, the use of FPGA in the ROM look-up table for data storage

VHDL语言教材-The teaching material of VHDL Language

mdio配置BCM5461，实现PHY初始化及通信相关寄存器的配置(mdio configure PHY)

在quartusII环境下采用对编解码芯片HD6408和HD6409驱动的方式实现曼彻斯特编解码(Environment in quartusII codec chip used on the HD6408 and HD6409-driven way to achieve encoding and decoding of Manchester)

DDR（双速率）SDRAM控制器参考设计，xilinx提供-DDR (double data rate) SDRAM controller reference design for Xilinx

FPGA驱动TCD1304AP线阵CCD，并经采集将数据通过串口传输至上位机(FPGA drives TCD1304AP linear CCD, and by collecting the data transmitted through the first bit machine serial)