FFT 32 BIT VHDL PROGRAM

利用康芯公司的FPGA芯片设计制作频率计，实现对频率的测量。(Kang core using FPGA chip design company frequency meter, realize the frequency measurements.)

讲述了dds直接数字频率合成的基本原理，同时用ＶＨＤＬ语言编写dds原代码用于生成正弦波，并在ISE开发平台进行仿真和MATLAB验证正弦波输出结果-described dds direct digital frequency synthesis of the basic tenets addition to the use of VHDL prepared dds source used to produce sine, and ISE development platform for simulation and verification MATLAB sine wave output

实用的程序代码，希望对大家有用，已经调试通过-Practical program code, in the hope that useful to everybody, has debugging through

verilog实现的“六进制约翰逊计数器”。(verilog implementation of the " six hexadecimal Johnson counters." )

VHDL实现 8051 CPU核 Oregano Systems 8-bit Microcontroller IP-Core-VHDL 8051 CPU nuclear Oregano Systems 8-bit Mic rocontroller IP-Core

说明：  串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。(source code, the code used veilog HDL language, and after I repeatedly verified.)

512×8bid的FIFO 含工程文件，基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII

verilog vga 图像处理(verilog vga)

关于语音通信信道调制的程序代码，是论文的仿真程序(About voice communication channel modulation code, the authors of the paper simulation program)

EV10AQ190A配置程序 EV10AQ190A configuration program(EV10AQ190A configuration program)