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AD9777_SPI_CONFIG
verilog ad9777 ad芯片的配置程序，SPI接口协议 16bit DA(Verilog ad9777 AD chip configuration program, SPI interface protocols for 16 bit DA)
- 2020-07-29 21:08:38下载
- 积分：1
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MultVerilog.pdf
Multiplication in Verilog code
- 2012-12-01 19:17:55下载
- 积分：1
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A signal can be stretched any one CLk the VHDL source code examples. See documen...
一个可以把信号拉长任意个CLk的VHDL源码例子。详见说明文档-A signal can be stretched any one CLk the VHDL source code examples. See documentation
- 2022-03-24 02:54:32下载
- 积分：1
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hapf
单相混合有源电力滤波器的设计与控制，在matlab中的仿真模型，功能效果很好。(The design and control of single-phase hybrid active power filter in matlab simulation model, the function works well.)
- 2012-12-11 16:17:23下载
- 积分：1
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clk_div3
在fpga中对于pll无法完成的分频，可采用计数方式，本例用状态机实现对时钟的奇数分频。(Pll in fpga can not be completed in the sub-frequency counting method can be used, in this case with the state machine to achieve an odd number on the clock frequency.)
- 2010-07-28 20:03:41下载
- 积分：1
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svpwm3
基於空間向量調變的開關法，在於載波做比較切出方波再送至開關讓馬達啟動(Based on the switching method of space vector modulation, the square wave is cut out for carrier comparison and sent to the switch to start the moto)
- 2019-01-04 16:07:37下载
- 积分：1
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lab_5
Introduction to learn laboratry with altera quartus II 9.1
- 2016-12-12 01:24:52下载
- 积分：1
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fft
FPGA实现FFT算法的源代码及工程文件，此工程为ISE工程项目。有详细的说明，可以运行。(FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.)
- 2013-10-12 17:21:32下载
- 积分：1
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on a serial data input timing will be based on output data using two procedures
关于一个串行数据输入 根据时序将数据分两路输出的程序 -on a serial data input timing will be based on output data using two procedures
- 2022-07-26 17:19:57下载
- 积分：1
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基于BASYS开发板的波形发生器和示波器设计
基于BASYS开发板的波形发生器和示波器设计，可以在显示器上显示波形，共有三角波方波锯齿波正弦波四种
- 2022-08-22 23:42:24下载
- 积分：1
