LCD 因其轻薄短小,低功耗,无辐射,平面 直角显示,以及影像稳定等特点,当今应用非常 广泛。CPLD(复杂可编程逻辑器件) 是一种具有 丰富可编程...

该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)

本压缩包，包换一个用verilog语言实现的huffman编码源程序，同时给出了众多论文和基础知识的文档资料，一应俱全。(The compression package, shifting one using huffman coding verilog language source code, and gives basic knowledge of many papers and documentation, everything.)

altera推出的基于它们fpga和cpld的构建嵌入式系统的新技术sopc的介绍。其集成在quartus II中-ALTERA due to launch them and they simply cpld Construction of the new Embedded System Technology sopc briefing. Its integrated into the Quartus II

基于FPGA的新型数据位同步时钟提取(CDR)实现方法-New FPGA-based data bit sync clock extraction (CDR) method

用VHDL编写的步进电机控制方法.供大家参考用.-prepared using VHDL stepper motor control methods. For your reference.

通过数码管和单片机的组合 制作成的数码管时钟程序(Through the combination of digital control and made ​ ​ into a single-chip digital clock program)

support for Coldfire m5441x processors.

NIOS II IDE 编程， FLASH测试程序，仅供参考。-NIOS II programming IDE, FLASH testing procedures, for information purposes only.

We present elliptic curve cryptography (ECC) coprocessor, which is dual-field processor with projective coordinator. We have implemented architecture for scalar multiplication, which is key operation in elliptic curve cryptography. Our coprocessor can be adapted both prime field and binary field, also contains a control unit with 256 bit serial and parallel operations , which provide integrated highthroughput with low power consumptions. Our scalar multiplier architecture operation is perform base on clock rate and produce better performance in term of time and area compared to similar works. We used Verilog for programming and synthesized using Xilinx Vertex II Pro devices. Simulation was done with Modelsim XE 6.1e, VLSI simulation software from Mentor Graphics Corporation especially for Xilinx devices.

8051的verilog内核，fpga里实现8051的话用得上-8051 Verilog cores, fpga achieve useful 8051 words