cycloneII ep2c5 ep2c8

modbus通讯必须的校验码生成器，可以直接使用(modbus crc16/8 free use)

In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.

LCD显示超级玛丽游戏2 (LCD display Super Mario game)

小家电常用芯片HT66F0185的UART 使用例子，已在产品使用(Small appliances commonly use UART chip HT66F0185 of example, has been used in products)

一个PS2 IP CORE(VHDL) for FPGA-A PS2 IP CORE (VHDL) for FPGA

说明：  SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)

3-8译码器，可以讲三位二进制输入转换为8中取1的输出信号(3-8 decoder, you can talk about the three binary input is converted to 8 of the output signal from 1)

VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)

调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据(4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data)

利用verilog编写的电梯程序，实现基本的电梯运行功能(Elevator program written by Verilog)