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crc16_8
modbus通讯必须的校验码生成器,可以直接使用(modbus crc16/8 free use)
- 2020-10-22 10:47:23下载
- 积分:1
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QPSK
In this case is a QPSK algorithm code for mapping the interleaved code, using VHDL language. This code provide the method of mapping the code by using QPSK algorithm.
- 2014-11-19 04:27:20下载
- 积分:1
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LCD_game2
LCD显示超级玛丽游戏2 (LCD display Super Mario game)
- 2012-09-03 21:58:48下载
- 积分:1
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ht66f0185-1
小家电常用芯片HT66F0185的UART 使用例子,已在产品使用(Small appliances commonly use UART chip HT66F0185 of example, has been used in products)
- 2020-10-09 16:27:34下载
- 积分:1
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一个PS2 IP CORE(VHDL) for FPGA
一个PS2 IP CORE(VHDL) for FPGA-A PS2 IP CORE (VHDL) for FPGA
- 2022-09-04 02:20:03下载
- 积分:1
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can总线
说明: SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)
- 2019-11-15 10:07:14下载
- 积分:1
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3-8
3-8译码器,可以讲三位二进制输入转换为8中取1的输出信号(3-8 decoder, you can talk about the three binary input is converted to 8 of the output signal from 1)
- 2009-07-16 17:23:30下载
- 积分:1
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VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)
VHDL_count 从 0 到 9 4 7 段 LED 显示器 (đếm 0 đến 9 hiển 施耐 4 带领 7 đoạn)
- 2022-01-20 23:11:51下载
- 积分:1
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interpolate4
调制信号后4倍内插的verilog代码,用于基带成型滤波器输入数据(4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data)
- 2017-04-20 15:52:09下载
- 积分:1
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电梯
利用verilog编写的电梯程序,实现基本的电梯运行功能(Elevator program written by Verilog)
- 2018-11-25 11:39:50下载
- 积分:1