VHDL Checkers Implementation by Ibrahim Elbouchikhi Amir Nader

通过代码控制音频编/解码硬件芯片WM8731， 通过按键控制音频输出的音量(Audio codec hardware chip WM8731 is controlled by code, and audio output volume is controlled by keys.)

使用verilog语言，滚动显示“verilog”字符串程序代码及相关说明(Using verilog language, scrolling display " verilog" string code and instructions)

verilog编写的基于CA算法的m序列发生器，其中验证了多种CA系数来实现m序列。(CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.)

说明：  关于计时器 verilog语言，采用arm架构的m3，可以直接应用于soc(About timer verilog language, USES the arm architecture of m3, can be directly applied to soc)

FPGA的fifo与dsp的emif接口测试程序(EMIF interface test program for FIFO and DSP of FPGA)

VHDL实现了IIS接口程序，在Quartus II 6.0上编译通过，在板子上可以读取IIS数据-IIS VHDL interface procedures, the Quartus II 6.0 compiled by the board can read data IIS

基于FPGA/EP2c5的开发板详细例程，内容丰富，简单易懂(Development board based on more routine FPGA/EP2c5, content rich, easy to understand)

六十进制计数器，VHDL编写的计数器，本科电子的可能有些实验可以用到(counter Possible experiments of undergraduate electronics can be used)

自适应滤波，对输入信号进行选择性的加权处理，使输出达到最优化，并且能够跟踪和适应系统和环境的动态变化(Least mean square，of the input signal processing, selective weighted output, and optimize can track and adapt to the dynamic changes of the system and environment)