VHDL Checkers Implementation by Ibrahim Elbouchikhi Amir Nader

代码实现了一个由32位寄存器组成的寄存器组，并有多个控制输入和两个输出，方便使用。(The code implements a 32-bit register consisting of registers, and there are multiple control inputs and two outputs, easy to use.)

同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料(Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references)

该项目是用VHDL编写的，并在Nexys2板套件的4个七段显示器中显示一个测微计的秒、分和小时。时间可以在开关0中停止，在按钮0中复位。显示方式与显示方式不同最小：分段到hr:min通过切换开关1

说明：  NAND FLASH的多个仿真模型，可以用于接口设计的测试(NAND FLASH multiple simulation model that can be used for the test interface design)

AV视频信号输入后，存入SDRAM中然后在PC上面进行显示的代码。-AV video signal input into the SDRAM in the PC and then display the code above.

user_logic_VGA_Controller，适合于DE2开发板，把这个文件夹放在工程目录之中，就可以在SOPC里直接添加VGA_Controller IP核了，很方便使用。-user_logic_VGA_Controller. suitable for Dictyophora development board, this folder on the project directory, it can be added directly SOPC Lane VGA_Controller IP core, very convenient to use.

Code VHDL for control VGA FPGA: Xilinx, Altera

68013与FPGA的通信，包含了固件程序与verilog程序(68013 and FPGA communication, including firmware and verilog program)

本白皮书探讨了在PCI Express的因素 技术可能会影响性能。它还 提供指导如何估算 的系统性能。(This white paper explores the factors in PCI Express technology may affect performance. It also provides guidance on how to estimate the system performance.)

files describe how to configure an ADV7180