vhdl source code for 8 bit datapath logic

利用VHDL语言实现8位到32位的双向数据转换-use VHDL 8-32 two-way data conversion

verilog alu 8bit for engineers

Enhanced Audio Project by Dixie Xue & Wei Zhang -Enhanced Audio Project by Dixie Xue & Wei Zhang

eDP接口TFT-LCD显示驱动原码（verilog+c）(eDP Interface TFT-LCD display driver source code (verilog+c))

说明：  该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)

A VHDL source code for testing the digits and the switches on a spartan 3 basys board

加密已经成为我们生活的一部分，我们

将FPGA设计仿真结果数据写入到txt记事本中，然后通过Matlab读取txt中的数据并显示图像(write the FPGA simulation result data into textbook,and read these data from textbook and display image in Matlab)

实现了UART的底层协议，加入了控制器，其波特率可以根据使用进行调整；发送模块、接收模块相互独立，互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)

实现千兆以太网数据发送，通过GMII接口向PHY写数据，控制PHY发送数据。(Implementation of Gigabit Ethernet data transmission, write data to the PHY through the GMII interface, control PHY data.)