VERILOG HDL 实际工控项目源码 开发工具 altera quartus2

完整的跑表设计，时，分，秒都显示，希望能对大家有用，谢啦(Complete stopwatch design, hours, minutes, seconds, show, hoping to be useful for everyone,)

Wimax矩阵的LDPC编码器，已通过modelsim仿真测试，并前在altera的FPGA板上通过测试,码率5/6，可进入代码内部修改参数，支持2/3,3/4其他2个码率，数据吞吐量为700M(Wimax based LDPC encoder, modelsim simulation passed, also passed on altera FPGA board, code rate 5/6, also support 2/3,3/4, throughout 700m)

说明：  彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)

this program performs multiplexing and demultiplexing

利用VHDL语言和模块化设计实现PCM编译码的功能，整体工程和代码全有。(PCM encode and decode by VHDL in Quartus2. )

串并转换程序，由串行输出转换为4位的并行输出-String and the conversion process, from the serial output is converted to 4-bit parallel output

SDRAM驱动器，自己项目利用的，已经经过实际验证(sdram controller)

vga接口的工程实现，基于altera环境，需要的可以-vga interface engineering implementation, based on altera environment, need to take a look at

DCT and Idct with vhdl and verilog

使用MATLAB完成CDMA系统的相关接收机，其中哈达码矩阵为128阶，仿真比特信噪比为-10DB-CDMA system using MATLAB to complete the relevant receivers, which Hadamard matrix of 128 bands, simulation-10DB-bit signal to noise ratio for