1. For the key input, please join the voice output circuit, representing the key...

个人搜集的各类Modelsim教程全集视频PDFWordPPT等.rar(Personal collection of all kinds of Modelsim tutorial video PDFWordPPT Complete Works, etc.. Rar)

一个用verilog写的串行传输到并行传输的程序，在quaters下编的-Using Verilog to write a serial transmission to the parallel transmission of the procedure, under the quaters

基于TCAM的高速路由查找，逻辑实现深度为32的内容查找，得到索引和命中指示(TCAM lookup based on a high-speed routing logic to realize the depth of content to find 32, get indexed and hit instructions)

VHDL实现的超前进位加法器-the VHDL-ahead Adder

用FPGA实现IIC通讯的主控端，最简化的代码，占用最小FPGA资源-Use FPGA to come ture the main control of the iic comunication, the most simple code and using the least FPGA resource

利用IIC接口的4路 ADC max1037，采集思路信号，通过在FPGA内部的构建DeltaSigma DAC软核，在VGA液晶显示屏上显示波形。 (IIC interface 4-way ADC max1037, collecting ideas signal the FPGA internal build DeltaSigma DAC soft-core VGA LCD display waveforms.)

说明：  bnn-fpga是FPGA上CIFAR-10的二进制神经网络（BNN）加速器的开源实现。 加速器针对低功耗嵌入式现场可编程SoC，并在Zedboard上进行了测试。 在编写CIFAR-10测试集中的10000张图像时，错误率是11.19％。(bnn-fpga is an open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA. The architecture and training of the BNN is proposed by Courbarieaux et al. and open-source Python code is available. Our accelerator targets low-power embedded field-programmable SoCs and was tested on a Zedboard. At time of writing the error rate on the 10000 images in the CIFAR-10 test set is 11.19%.)

moore 状态机的一个简单的事例，初学者很好的地实例！-moore state machine of a simple example for beginners to very good example!

说明：  一个PN序列发生器，大M序列，供参考学习，(A PN sequence generator, the M series, for reference study,)

VHDL硬件描述语言作业-VHDL hardware description language operations