altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。...

HLD开发语言ADHL介绍。ADHL是ALTERA公司开发的硬件描述语言，也是一种较为流行的开发工具。是介绍AHDL的入门培训资料。-HLD development language ADHL introduction. ADHL is ALTERA developed hardware description language, but also a more popular development tools. AHDL is the introduction of induction training information.

说明：  how to come ture a costas loop in FPGA with verilog,it is very useful on project

golomb编码，用于无损图像压缩等，基于quartusii平台。-golomb coding for lossless image compression, based on the platform quartusii.

基本的操作代码,a0-a7是八个信号输入端，a7的优先级最高，a0的优先级最低，当a7输入低电平0时，其他输入无效，编码输出y2y1y0=111；如果a7无效，而a6有效，则y2y1y0=110；

基于FPGA的快速傅里叶变换。使用ISE软件以及MATLAB验证。(FFT based on FPGA)

Giao tiep Univesan ...

基于NIOS的CF卡应用(包括了软件和硬件),ALTERA的IP库中只提供了底层的硬件寄存器描述头文件.这是个基于IP核HAL的软件,以及相应的硬件设计示例.-NIOS based on the CF card applications (including the software and hardware), ALTERA the IP library provides only the bottom of the first document describes the hardware registers. This is a HAL-based IP core of the software, hardware design and the corresponding sample.

一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)

基于FPGA的16*16点阵中文LED显示，另带有几个简单的中文汉字的点阵数据。(FPGA-based 16* 16 dot matrix Chinese LED display, and the other with a few simple lattice data Chinese characters.)

verilog实现mp3解码程序，包括testbench(mp3 decoder verilog implementation procedures, including the testbench)