altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。...

通用存储器VHDL代码库,The Free IP Project VHDL Free-FIFO, Quartus standard library. -generic VHDL code for memory, The Free Project VHDL IP Free-FIFO, Quartus standard library.

CODE_VHDL_COUNTING 0 到 9 (慈 0 đến 9 Đếm hiển đoạn 施耐 1 带领 7)

Verilog HDL实现的I2C Slave模拟-achieve the Verilog HDL simulation I2C Slave

直接频率合成，Quicklogic提供,部分源文件是Quicklogic 专用文件-direct frequency synthesis, pioneered provide some source document is dedicated ESP

是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。-is a VHDL language with the PWM procedures can be used to facilitate connections and nios, nios to achieve a functional extension.

利用LMP的20bit counter,比自带的cout进位要快的多。已经同错综合和时序仿真。-LMP

it is used to compile codec

cic_dec_8_three CIC 文件的ＶＨＤＬ-cic_dec_8_threeCIC documents VHDL

温度传感器实验，将温控芯片的温度信号通过fpga用数码管显示(temperature display)

基于FPGA的红外图像预处理系统的研究与设计，给fpga工程技术人员一个参考-FPGA-based infrared image preprocessing system and design, engineering and technical personnel to fpga a reference