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ExpectedBoardDetails1.txt
Use full for knowing board details while making projects on FPGA and matlab simulations
- 2013-11-20 17:47:58下载
- 积分:1
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Cmos 全加法器使用绝热逻辑
绝热电路都是使用"可逆逻辑"的低功耗电路以节省能源。与传统的CMOS电路,在开关过程中消耗能量,不同绝热电路试图节约费用由以下两个关键的规则:
永远不会打开一个晶体管时电压源之间
- 2023-04-29 04:00:02下载
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系统设计
基于PCF8591数模转换和DDS技术的信号发生器系统设计(Design of Signal Generator System Based on PCF8591 Digital-to-Analog Conversion and DDS Technology)
- 2020-06-21 02:20:01下载
- 积分:1
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The source code for the Nios II development of an example, the main demonstratio...
本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。
本示例十分经典,对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.
- 2022-06-27 00:21:06下载
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用CPLD驱动扬声器实现音乐的播放,程序是用VERILOG写的,
用CPLD驱动扬声器实现音乐的播放,程序是用VERILOG写的,-CPLD driver speakers with music player, the program is written in VERILOG,
- 2022-03-20 12:37:01下载
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USB_xilinx_vhdl
说明: Giao tiep Univesan ...
- 2020-06-20 03:00:02下载
- 积分:1
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M序列?¨
生成一个M伪随机序列码,在ISE平台上可跑通(Generate an M Pseudo-Random Sequence Code which runs on ISE platform)
- 2019-05-05 15:54:38下载
- 积分:1
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UART
字长可以简单调整,即可实现任意字长UART通讯(The word length can be simply adjusted to achieve any word length UART communication.)
- 2018-07-09 22:06:02下载
- 积分:1
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FIFO
This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)
- 2013-10-04 00:41:42下载
- 积分:1
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fpga数码管显示
让你EJ疼没人开门吗维护和输入热火男的竟然也可以看看一份心疼你身边女人很多好的主人你让他愤怒和难题太难太难太难输入你的人难道她和他人的烦恼的童年听到她赫然发红包少年人反而能认识的男人的法人俄方的人体内
- 2023-01-03 09:40:17下载
- 积分:1