设计了一个异步时钟域间进行通行的模块，并采用Modelsim进行仿真验证，仿真结果满足预期的目的。...

在硬件方面十进制到二进制将不需要采用加法器计算的方式，大大减少了计算时间。

使用verilog硬件设计语言在FPGA板子上STOPWATCH 秒表设计。(Using verilog hardware design language STOPWATCH stopwatch design on FPGA board.)

RS232接收程序 无奇偶校验位 并行输出8位数据与data_ready数据准备好信号(RS232 receive procedures without parity 8-bit parallel output data and data ready signal data_ready)

用vhdl语言编写的16bit的REG代码，以及iv，not and2，rca，fa，alu，acc，lfsr，mux21.

在利用FPGA的并行处理能力应对高速数据和去做复杂的数据处理时，对一些较为复杂或者重复性工作模块多的情况下，算法资源就需要进行预评估。有效的资源预评估不仅可以在芯片选型上有益，还可以对程序有较详细的估计，在硬件不变的前提下能够选择更好的算法优化。本文着重在Harris算法在FPGA的实现以及在移植之前对其占用的FPGA资源进行预评估。(Response to high-speed data and do complex data processing in the FPGA parallel processing capabilities, to cope with some of the more complex or repetitive tasks module，it is necessary to pre-assessment algorithm resources. Resources pre-assessment can not only be useful in the chip selection, but also be a more detailed estimate of the program to be able to choose a better algorithm optimization in the same premise hardware. This article focuses on the pre-assessment in the Harris algorithm in the FPGA implementation and its FPGA resources occupied prior to transplantation.)

Diagram and how-to-make instructions pack of 6 diferent Amplifiers

VHDL实用教程（潘松）,非常经典讲解VHDL语言，包含基本语法及实例。-VHDL Practical Guide (Pan Song), is a classic on the VHDL language, including basic grammar and examples.

基于FPGA的红外图像预处理系统的研究与设计，给fpga工程技术人员一个参考-FPGA-based infrared image preprocessing system and design, engineering and technical personnel to fpga a reference

TLC5510的驱动程序，采用Verilog语言编写(TLC5510 driver, the use of Verilog language)

verilog实现的简易通用型CPI接口-verilog easy to achieve CPI general-purpose interface