设计了一个异步时钟域间进行通行的模块，并采用Modelsim进行仿真验证，仿真结果满足预期的目的。...

Verilog写的 8 位超前进位加法器-Verilog write 8-bit CLA

乒乓RAM静态随机存储器的控制，用于解决数据流连续存储问题。(Ping pong RAM static random access control, to solve the problem of continuous data flow storage.)

基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal

IT IS THE DP MEMORY MODULE. IT CONTROLS THE DP MEMORY

采用双线性变换法设计IIR数字滤波器设计的c代码，包括低通、高通和带通(Document recording the design of IIR digital filter c code)

异步串口通信口在FPGA实现，功能有（1）串行数据接收的同步控制；（2） 串行数据发送的同步控制-asynchronous serial communication port of the FPGA, function (1) serial data receiver synchronization control; (2) the transmission of serial data synchronization control

VHDL的基本语法，应用，建模，编程示例等...(Introduction to VHDL basic syntax, applications, modeling, programming example and so on ...)

5604FPGA驱动，能显示数字（5604里面为4个595）(5604 FPGA driver, able to display digital (5604 contains 4 595))

若农场路无车辆，则在高速路保持绿灯。在探测农场路有车辆，高速路上的交通灯应由绿到黄，再到红，并允许农场路方向灯变绿，绿灯亮一段时间，由绿变黄再到红。(If there is no vehicle on the farm road, keep the green light on the highway. There are vehicles on the farm road, the traffic lights on the high speed road should be green to yellow, and then red, and allow the farm road lights to turn green, the green light for a period of time, from green to yellow, then to red.)

基于VHDL语言的DPLL电路的设计，给出了设计方案和部分源代码 (DPLL)