设计了一个异步时钟域间进行通行的模块，并采用Modelsim进行仿真验证，仿真结果满足预期的目的。...

Verilog_HDL源码 -Verilog_HDL source Verilog_HD L FOSS Verilog_HDL FO

cyclone和cyclone2用在5v系统里使用方法,使得FPGA芯片在5V系统中兼容-cyclone and cyclone2 system used in the use 5v, making FPGA chip compatible with the 5V system

基于VHDL的数字频率计的设计.pdf 基于VHDL的频率计设计 很好用的 希望要用的同志来下载 (基于VHDL的频率计设计 很好用的 希望要用的同志来下载 )

改变学习板上的2个电位器对应的2段模拟输入，实现模拟输入，学员观察数码管的数字变化情况,通过改D[4]的值，实现模拟输出.(Changing the learning board two potentiometers corresponding paragraph 2 analog inputs, analog inputs, digital tube digital trainees observe the changes, by changing D [4] value for analog output.)

华为经典设计全套入门技巧，面试经验，设计技巧(Huawei Classic Design Complete Introduction Skills, Interview Experience, Design Skills)

system gen & accel dsp 培训资料-system gen & accel dsp

8位并行输入的数转换成串行输出，是基于高级硬件编程语言VHDL编写的。(8-bit parallel input into serial output digital conversion is based on the high-level hardware programming language VHDL prepared.)

乘法器的vhdl语言描述.本人调试已经通过-Multiplier described in VHDL language. I have been through the debugging

给出了SVPWM算法的详细FPGA实现方法！(A detailed FPGA SVPWM algorithm to achieve the method!)

4 seg display, button debouncer, and controller for parking meter