设计了一个异步时钟域间进行通行的模块，并采用Modelsim进行仿真验证，仿真结果满足预期的目的。...

基于Verilog的小波滤波器程序设计的总结文档。(Verilog based wavelet filter program design summary document.)

一个可以综合的Verilog 写的FIFO存储器 内附文档说明-a comprehensive Verilog can write FIFO memory attached document shows

应用VHDL语言编写交通灯的控制程序。 熟悉该语言的基本用法。-Application of VHDL language of the control procedures of traffic lights. Familiar with the basic use of the language.

用FPGA实现的VGA/LCD显示的相关知识,包含了程序的主要结构和主要功能模块的实现过程-Using FPGA to achieve the VGA/LCD display relevant knowledge, including the procedures for the main structure and main function modules of the realization process

说明：  LVDS De-serialization

多相抽取滤波器。分四相，两倍抽取，采用16阶FIR滤波器实现(Polyphase decimation filters. Divided into four phases, extracted twice using 16-order FIR filter implementation)

这是基于MIMO-OFDM的同步算法研究的源程序。本程序采用的极大似然估计的方法。(This is based on MIMO-OFDM synchronization algorithm source code. The program uses the method of maximum likelihood estimates. )

FPGA驱动VGA接口显示字符 -FPGA-driven interface VGA display characters

IEEE Standard for Verilog 2005

用VHDL语言在CPLD上实现串行通信-using VHDL on the CPLD Serial Communication