网站首页

登录

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0],...

于 2022-06-13 发布文件大小:4.60 kB

 0  183

下载积分: 2 下载次数: 1

我要下载

代码说明：

Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.

下载说明：请别用迅雷下载，失败请重下，重下不扣分！

发表评论

0 个回复

延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块...
延迟线模块的verilog代码，延迟线模块是数字电路设计常用的模块-Delay-line module Verilog code, delay-line module is commonly used in digital circuit design module

2022-08-09 02:38:35下载

积分：1
gtx_drp
高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接(High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link)

2021-01-19 22:38:43下载

积分：1
收集了目前关于FPGA设计的论坛，大家如果有什么疑问，可以到这些论坛上求助。...
收集了目前关于FPGA设计的论坛，大家如果有什么疑问，可以到这些论坛上求助。-The collection of the current design of the forum on the FPGA, there is little doubt if the U.S. can go to for help on these forums.

2023-07-21 21:55:02下载

积分：1
ep2c5 实现逻辑门 verilog语言，quartus 2 仿真
ep2c5 实现逻辑门 verilog语言，quartus 2 仿真-ep2c5 the realization of logic gates verilog language, quartus 2 Simulation

2022-09-08 22:10:08下载

积分：1
CPU流水线设计报告
说明： CPU课程设计要求以FPGA开发平台为例，分析 CPU 设计的流程与仿真。本次开发使用的硬件描述语言是 Verilog 语言，使用的指令系统是一个以 MIPS 指令集为子集的指令系统，共 22 条指令，所用的设计仿真软件Modelsim。(CPU curriculum design requires FPGA development platform as an example to analyze the process and Simulation of CPU design. The hardware description language used in this development is Verilog language, and the instruction system used is an instruction system with MIPS instruction set as a subset, with 22 instructions in total. The design simulation software Modelsim is used.)

2020-12-24 12:09:05下载

积分：1
8832135
一个具有“百分秒，秒，分”计时功能的数字跑表，可以实现一个小时以内的精确至百分之一秒的计时。数字跑表的显示读者可以通过编写数码管显示程序来实现，本训练只给出数字跑表的实现过程。读者还可以通过增加小时的计时功能，实现完整的跑表功能。(A " percentage of seconds, seconds, minutes," digital stopwatch timer can be achieved within an hour of precision to the hundredth of a second time. Digital stopwatch readers can display the digital display through the preparation of procedures to achieve, given the training is only the realization of the process of digital stopwatch. Readers can also function to increase hours of time to achieve full stopwatch function.)

2009-04-09 13:20:35下载

积分：1
spi_slave
FPGA实现SPI接口的从机功能，接收和发送全双工运行，接收到的数据以八位LED灯显示(FPGA to achieve the SPI interface the machine function, receive and send full-duplex operation, the received data to eight LED lights)

2021-01-07 19:28:52下载

积分：1
Farrow
matlab代码，利用Farrow结构设计分数延时滤波器，滤波器阶数和个数可分别进行设置，利用最大最小准则近似。(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)

2021-03-28 22:29:11下载

积分：1
texample1
32-bit shifter, shifter, 32-bit.Very goog as a study file.

2015-10-24 09:44:53下载

积分：1
hdl-master
ADI ad9361 vivado 下源代码(ADI ad9361 vivado source code)

2015-08-30 21:39:28下载

积分：1

696516资源总数
106914会员总数
0今日下载