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xilinx_dna_read
该模块已经成功运用在xilinx xc6slx45t,xc6slx75t多个产品中,经过实践证明,采用dna及其加密算法加密是一种成本低廉(无需另外加密芯片)可靠的加密手段。Xilinx Spartan-6 FPGA读取DNA数据并进行比较,产生比较结果信号输出。附带有xilinx DNA.ppt说明及调试注意事项。(The module has been successfully used in xilinx xc6slx45t, multiple xc6slx75t products, proven, and the encryption algorithm uses dna is a low-cost (no additional encryption chip) reliable means of encryption. Xilinx Spartan-6 FPGA reads the data and compare DNA to produce a comparison result signal output. Xilinx DNA.ppt comes with instructions and commissioning notes.)
- 2020-10-15 20:07:29下载
- 积分:1
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bit7_Binary_to_BCD_LED
二进制转十进制BCD码 Verilog语言 quartusII(Binary to decimal BCD code Verilog language quartusII)
- 2013-09-14 16:49:39下载
- 积分:1
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可编程ASCII
说明: 写出13个简单的Verilog demon,适合初学者观摩学习。配合实验报告,食用更佳。(Write 13 simple Verilog demon, suitable for beginners to observe and learn. With the experimental report, it is better to eat.)
- 2020-12-28 18:59:02下载
- 积分:1
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双向使用VHDL仿真环境转移登记环节
用vhdl实现双向移位寄存器 仿真环境MAXPLUS-II,QUARTUS--bidirectional use VHDL simulation environment shift register Segments-II, QUARTUS-
- 2022-03-20 23:34:56下载
- 积分:1
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demo6-beep
说明: demo6 蜂鸣器实验
蜂鸣器演奏音乐(demo6 buzzer buzzer experiment playing music)
- 2020-12-27 22:59:02下载
- 积分:1
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61EDA_C1202
Altera大学计划程序包,基于Nios II的源代码(Altera University program package, based on the Nios II source code)
- 2008-08-21 14:46:39下载
- 积分:1
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vhdl写的ds18b20程序,相互交流
vhdl写的ds18b20程序,相互交流-vhdl written ds18b20 procedures, mutual exchange
- 2022-03-19 16:58:50下载
- 积分:1
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clk_generator
时钟分频代码,PWM产生 RTL 源代码。(clock divider,PWM generator RTL Source Code)
- 2013-08-18 09:29:42下载
- 积分:1
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shudianshiyan
数字电路与逻辑设计实验编程,包含多功能电子钟程序,实用,简易(Digital circuits and logic design experiments programming, including multi-function electronic clock procedures, practical, simple)
- 2011-07-07 08:52:13下载
- 积分:1
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dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
- 2022-12-25 17:55:03下载
- 积分:1