贪吃蛇文件

用VERILOG实现一个被除数为8位、除数为4位的高效除法器(With VERILOG implement a dividend for the 8-bit, 4-bit effective divisor divider)

说明：  fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)

三相PWM整流，实现功率双向流动,可保持直流侧电压稳定(three-phase PWM rectifier, power can bidirectional flow ，can maintain the stable DC voltage)

TCM解码，VHDL代码，是我在工作中做的工程代码，时序稳定，里面有syn以及软判决的算法，经典-TCM decoder, VHDL code, yes, I do work in the project code, timing stability, There are syn and soft-decision algorithm, classic!

展位的乘法算法 is a 乘法算法两者相乘得两个签名二进制 请点击左侧文件开始预览 ！预览只提供20%的代码片段，完整代码需下载后查看 加载中 侵权举报

基于verilog的RS编码器 绝对实用(Based on the RS encoder verilog absolute utility)

FM接收机 基于FPGA的调频收音机的设计 用VEIRLOG语言编程，利用QUARTUSii与MODELSIM联合仿真(FM receiver on FPGA FM receiver design With VEIRLOG language program, use QUARTUSii and MODELSIM joint simulation)

说明：  本代码是控制DS1302的VHDL代码，浅显易懂，方便修改，注意看data sheet，保证时钟和各个延迟满足要求即可(This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays)

4位全加法器的modelsim工程带testbench(Four full-adder modelsim project with testbench)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动跟踪(System Generator based image processing engineering, multimedia processing on FPGA source, video-based motion tracking)