贪吃蛇文件

VHDL硬件描述语言与数字逻辑电路设计―― VHDL语言的基本知识和设计逻辑电路的基本方法及NAX的使用-VHDL hardware description language and digital logic circuit design

本程序用于实现OFDM信道估计的LS算法的硬件仿真，基于FPGA开发的VHDL编写，给出了各模块的仿真波形图，供大家交流参考。

读取AD7895 的12位ADC转换值，连续读取方式，采样速率为20mS 一次。(Read the 12 bit ADC conversion value of AD7895.)

this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on sr and d flip flop using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

基于DDS的信号源设计（包括三角波、正弦波、方波）(Design of signal source based on DDS)

基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using

说明：  LTE is an abbreviation for Long Term Evolution.

本例设计一个码率为500kb/s，字长为8 位、帧长为128 个字、帧同步码为EB90H 的PCM 采编器。用VHDL语言实现的。(This designs a code to lead for the 500 kbs|s, the word is long for 8, the growing is synchronous code of for 128 words and for the EB90 H of PCM adopt to weave a machine.Use what VHDL language carry out. )

本源码是用Verilog编写的12位移位相加乘法器的设计源码，开发软件为MAX+PLUS，已经测试通过。(The Verilog source code is written in the sum of 12-bit shift multiplier design source code, developing software for the MAX+ PLUS, has been tested.)

用verilog实现sobel边缘检测算法(sobel edge detection with verilog language)