Cordic 算法实现

24,60,100进制的计数器，还有数字时钟，欢迎下载哦~-24,60,100 229 of the counter, digital clock also welcome to download oh ~

许多非常有用的 Verilog 实例: ADC, FIFO, ADDER, MULTIPLIER 等(many very useful Verilog examples : ADC, FIFO, ADDER, MULTIPLIER etc.)

1024点FFT快速傅立叶变换,(vhdl代码)-1024-point FFT vhdl

VHDL语言实现摄像头的捕捉和采集,通过仿真验证，很好哈-vidicon s catch and collection in VHDL

LPC4357开发板采用ARM的Cortex-M4微控制器LPC4357。内置一个ARM Cortex-M0协处理，CPU运行频率高达204MHz，片内集成1MB Flash和36KB SRAM。开发板采用独立核心板设计，核心板集成64MB SDRAM、128MB NAND-Flash、4MB SPI-Flash。核心板上的摄像头接口可直接连接各种型号的摄像头，两侧160P排针接口引出了除EMC总线外的LPC4357芯片所有功能管脚。 开发板提供丰富的外设接口，包括以太网、液晶屏、摄像头、USB-Host、USB-OTG、SD卡、RS232、RS485、CAN、耳机、麦克风、温度传感器、AD/DA、JTAG仿真器等。此外，开发板提供一个14P扩展接口，包括1路UART、1路SPI、1路I2C、4个IO、3.3V、5V，可以很方便的扩展自己的外围电路。(DS-LPC4357 development board using the Cortex-M4 microcontroller LPC4357 ARM s. A built-in ARM Cortex-M0 co-processor, CPU operating frequency up to 204MHz, 1MB Flash and 136KB SRAM integrated on chip. Development board using an independent core board design, the core board integrates 64MB SDRAM, 128MB NAND-Flash, 4MB SPI-Flash. Camera core board interface can be directly connected to various types of cameras, both sides 160P pin interface leads to the outside of the bus in addition to EMC LPC4357 chip all the functions of the pins. Development board provides a rich set of peripheral interfaces, including Ethernet, LCD screen, camera, USB-Host, USB-OTG, SD card, RS232, RS485, CAN, headphone, microphone, temperature sensor, AD/DA, JTAG emulator, etc. . In addition, the development board provides a 14P expansion interfaces, including one-way UART, 1 road SPI, 1 channel I2C, 4 个 IO, 3.3V, 5V, can easily expand their peripheral circuits.)

Cadence_manual_1.2.pdf

说明：  基于CycloneV FPGA与电阻网络的数模转换器代码，能够实现键控更改频率，通过ROM IP核存储波形数据。(Digital to analog converter code based on cyclonev FPGA and resistance network can realize keying change frequency and store waveform data through ROM IP core.)

说明：  简单uart，verilog语言编写，已经经过测试，有需要的可以看看(Simple uart, Verilog language, has been tested, you can see if you need it)

说明：  displayport 参考设计，可以对比自己工程做验证，另有参考设计XAPP1178未找到，采用方案为DP159 + Artix7 FPGA(xilinx displayport sink design)

ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER