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This an interpolating by 2 half
This an interpolating by 2 half-band filter with 79 taps (40 none-zero coefficients).
- 2022-03-06 22:11:21下载
- 积分:1
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PCI IP核vhdl源码,Xilinx原版
PCI IP 核 Xilinx原版,很好用,国际知名公司Xilinx原版,值得信赖
- 2023-05-01 04:45:04下载
- 积分:1
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用verilog语言写的串口通信程序,包括收发两个模块,可用于FPGA的通信中,可通过程序设置收发的位数,有很好的扩展性....
用verilog语言写的串口通信程序,包括收发两个模块,可用于FPGA的通信中,可通过程序设置收发的位数,有很好的扩展性.-Verilog language used to write serial communication program, including the sending and receiving two modules can be used for FPGA communications, you can send and receive through the program to set the number of bits, there is a very good scalability.
- 2022-06-17 10:57:04下载
- 积分:1
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shift_reg
Shift reg in vhdl, a first example to start
- 2011-03-27 10:35:25下载
- 积分:1
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通过vhdl实现ls138硬件功能 通过vhdl实现ls138硬件功能
通过vhdl实现ls138硬件功能 通过vhdl实现ls138硬件功能 -the description of ls138 in vhdl
- 2022-07-14 19:56:28下载
- 积分:1
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dgnszsz
多功能数字钟,在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)
- 2013-09-20 10:20:31下载
- 积分:1
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Code-Verilog
this is code verilog
- 2012-05-09 22:02:56下载
- 积分:1
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对于一个扫描程序的编写进行VHDL开发环境
maxplus2为开发环境 vhdl编写的 扫描 程序-maxplus2 VHDL development environment for the preparation of a scanning program
- 2022-03-14 13:51:23下载
- 积分:1
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dds(1)
基于DDS的信号发生器设计。DDS,FPGA,Verilog。(Design of signal generator based on DDS.DDS,FPGA,Verilog.)
- 2017-07-11 16:36:38下载
- 积分:1
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LDPC_Encoder
verilog 编写的ldpc编码,含有两个文件(LDPC written by Verilog)
- 2021-03-08 19:19:28下载
- 积分:1