vhdl testbentch 编写模板。非常实用

用vhdl 语言实现138译码器，用vhdl 语言实现138译码器，(vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl )

异步FIFO的设计 包括testbench 已调试成功-Asynchronous FIFO design includes testbench debug success has been

altera的关于对数计算的IP core。-altera calculated on the logarithm of the IP core.

基于Basys3的数字钟实例，主要用于Basys3、vivado开发环境入门。源码使用VerilogHDL(Based on digital clock instance Basys3, mainly for Basys3, vivado development environment started. Use Code VerilogHDL)

该模块采用cordic算法计算正弦和余弦，并采用参数化方式实现。 ；包中存在其他模块。

8*8键盘矩阵 用作单片机 8*8键盘矩阵 用作单片机 8*8键盘矩阵 用作单片机-8* 8 keyboard matrix used as a microcontroller 8* 8 keyboard matrix used as a microcontroller 8* 8 keyboard matrix used as a microcontroller 8* 8 keyboard matrix used as a MCU

硬件设计VHDL学习100例(站长推荐)-VHDL hardware design study of 100 cases (chief recommended)

VHDL语言实现时钟程序，用fpga开发板试过后，能够执行-VHDL Pang Sung-wife of mother

This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.

Use full for knowing board details while making projects on FPGA and matlab simulations