vhdl testbentch 编写模板。非常实用

LFSR模块，单个模块，实现移位寄存器，生成测试用pattern-LFSR

this code to input 8 different data and make them out sequentialy

FPGA上的一个半加器实例程序，通过测试，可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)

说明：  该模块实现了FPGA的uart串口收发功能(The module realizes UART serial port transceiver function of FPGA)

一个简单的uvm搭建的ahb简单实例,包含了各个组件以及编译的运行的脚本(one sample example about ahb，include every component and compile script)

Efficient_Digital_Implementation_of_Extreme_Learning_Machines_for_Classification

本程序为四路抢答器verlog HDL语言工程实例。(This program is four Responder verlog HDL language engineering examples.)

该代码完成了利用IIC总线接口，对HDMI芯片的EDID码进行配置的功能，已经验证在XILINX ML605开发板可用。

用VHDL语言实现一Mealy型时序电路，并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)

4X4 KEYPAD 的输入位数计数器，可以自己定义输入的位数-4x4 KEYPAD median counter input, input their own definition of the median