vhdl testbentch 编写模板。非常实用

改进的DCT算法设计，veriloghdl实现-Improved DCT algorithm design, veriloghdl realize

数字通信系统相移键控CPSK信号和差分相移键控的调制与解调的VHDL代码(Phase shift keying digital communication system CPSK signals and differential phase-shift keying modulation and demodulation of the VHDL code for)

Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA. Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit! The UART controller was simulated and tested in hardware.

很多VHDL例子，没有测试，供大家参考-VHDL many examples, there is no test, for your reference

说明：  DA芯片输出控制 SPI协议 只写不读 FPGA用 verilog(DA-chip SPI protocol output control does not read write-only FPGA with verilog)

说明：  FPGA实现PLL锁相环，输出不同频率的时钟控制信号。(FPGA realizes PLL and outputs clock control signals of different frequencies.)

六十进制计数器，显示0到60.可以用数码管显示。(Six decimal counter 0-60 can use the digital display.)

说明：  CAN VHDL Code. Behavioral implementation of CAN bus interface.

汽车尾灯控制系统 汽车尾灯控制器的VHDL程序实现 -car taillight control system controller car taillight VHDL program

 音频信号先经过由运放和电阻组成的50Ohm阻抗匹配电路以满足输入阻抗50 Ohm的系统要求，这样方便信号功率的计算。为了保证所处理的信号被不失真的采样，信号还要通过截止频率为10Khz的抗混叠低通滤波器。最后为了AD能正确的采样，信号还要通过信号抬高电路。 经过12位A/D转换芯片MAX144转换后的数字信号经由基于FPGA的NIOSII处理器进行FFT变换和处理，分析各个频率点的功率值，并将这些值显示在LCD上。 该源代码就是fft变换的源代码