altera的关于对数计算的IP core。

当时是用于课程设计而编写的代码，经过的运行没有错误。精确率很高。基于FPGA的数字频率计VHDL源码（精确到1.1hz至20.0mhz）

The objective of the labs today is to give you a basic understanding of FPGA design and enough experience to begin your own FPGA design with the ISE 10.1 tools and the Xilinx Spartan-3A DSP 1800A Starter Kit.

LED灯、跑马灯的显示源程序，包括对代码的说明(Display source code LED lights, marquees, including the code specification)

4位ALU,有两个4位输入，4位输出实现逻辑运算和算术运算，逻辑与或非，加1，减1等等功能(4 ALU, logical and arithmetic operations)

ac97 VHDL core

说明：  FSK VHDL FSK调制与解调VHDL程序及仿真(FSK VHDL )

基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考-FPGA-based high-performance 32-bit floating-point nuclear FFTIP development, engineering and technical personnel for reference fpga

一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl

vhdl的仿真 quartus 2的flv视频 -VHDL simulation of the flv video quartus 2

长帧同步时钟的产生， 源码程序，实验好用(Long frame synchronization clock generation, source program, easy to use experimental)