VHDL hardware design study of 100 cases (chief recommended)

基于FPGA的1602时钟显示,驱动1602显示时钟,矩阵键盘调时(1602 FPGA-based clock display, clock display driver 1602, when the transfer matrix keyboard)

说明：  FPGA锁相环实验： 顶层文件加底层IP文件构成 top中例化ip核pll(Experiment of Phase-Locked Loop Based on FPGA)

SOPC基于MATLAB与DSP Builder设计技术 实验使用说明，非常详细，易于上手(dsp builder)

握手程序，可以完美实现跨时钟域的数据传输(handshake and testbench，verilog HDL)

设计一个简单的FIR滤波器，并按要求确定滤波器的系统函数。(Design a simple FIR filter, and determine the filter according to the requirement of system function.)

基于FPGA的多波形发生器 基于FPGA的多波形发生器-FPGA-based multi-waveform generator based on multi-FPGA Waveform Generator

实现十字路口简单交通灯的verilog hdl源代码,可以实现-Realize a simple traffic lights at the crossroads of the verilog hdl source code, can be achieved

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NIOS II IDE 编程， uart_txd测试程序，仅供参考。-NIOS II IDE programming, uart_txd testing procedures, for information purposes only.

100个VHDL的例子-100 examples of VHDL