VHDL hardware design study of 100 cases (chief recommended)

用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)

DDR SDRAM控制器verilog代码及中文说明文档,对DDR开发很有用的哈。-Verilog source code for DDR SDRAM controler design,including guide book in chinese.

camping checklist for outback campers. A must for deep forest hikers.

altera usb 下载线DIY完全资料-altera usb blaster

VHDL语言教材-The teaching material of VHDL Language

dct and idct vhdl code

ARM处理器的IP核，用verilog编写的，对处理器和相关的CPU架构知识有很大帮助。(ARM processor IP core, written in verilog processor and CPU architecture knowledge.)

FPGA在直流电机调速中的应用,利用fpga进行PID闭环控制(tell us speed control for DC motor by FPGA,use fpga for PID circle control)

用组合逻辑实现循环除法器。稳定、安全、可靠。(Combinational logic loop divider. Stable, secure, and reliable.)

这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。 (Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.)