VHDL hardware design study of 100 cases (chief recommended)

说明：  SPI协议的芯片验证VIP,用UVM搭建平台验证代码(Chip verification VIP of SPI protocol, build platform verification code with UVM)

一个交通灯的vhdl语言实现 用 ＶＣ的　　１．在指定的文件夹内查找某个文件 　　　　　２．获取系统文件夹的路径， 要求显示windows system temp 当前目录的路径 Ｃ语言　　跳马问题：在５＊５的棋盘上，以编号为１的点出发，按日只跳马，要求不重复地跳所有位置，求出符合规则所有跳马的方案 　　　　１　　６　　１５　　１０　　２１ 　　　　１４　９　　２０　　５　　　１６ 　　　　１９　２　　７　　　２２　　１１ 　　　　８　　１３　２４　　１７　　４ 　　　　２５　１８　３　　　１２　　２３ -a traffic light VHDL language of a VC. The designated folders to search within a document 2. Access to the system folder path, requested that the current windows system temp directory path C language vault : 5* 5 in the chessboard to the No. 1 starting point, the only daily vault and asked not to repeat all locations to jump to get in line with all rules of the program vault 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23

实现一个简单的电子钟，其时间（时，分，秒）可以设置和更改，设置和更改的同时不会影响其他显示的变化（相互独立）。-achieve a simple electronic bell, the time (hours, minutes and seconds) can set and change, Settings and change will not affect the other shows the change (independent).

fir低通滤波器 用于dspbuilder pll：25nss data 400khz sin 10.8khz 已通过测试。 (fir low pass filter for dspbuilder pll: 25nss data 400khz sin 10.8khz has been tested.)

C语言写得FIR滤波器代码，简单实用，是学习滤波器设计的好材料，附带PPT滤波器设计说明(C language written FIR filter code, simple and practical, is a good learning materials of filter design, with PPT filter design )

说明：  通过一个计数器来实现输出信号的占空比要求，可以将duty_cycle分配到拨码开关上,LED分配到发光二极管上,然后调节拨码开关,即可看到LED的亮度发生变化.(The duty cycle of the output signal can be assigned to the dial switch by a counter, and the LED can be assigned to the light emitting diode. Then the brightness of the LED can be seen by adjusting the dial switch.)

说明：  misp顶层文件，verilog实现misp架构，并且支持modelsim仿真(Verilog implements MISP architecture and supports Modelsim simulation)

数字通信系统相移键控CPSK信号和差分相移键控的调制与解调的VHDL代码(Phase shift keying digital communication system CPSK signals and differential phase-shift keying modulation and demodulation of the VHDL code for)

一个可用的很不错的DDS 频率合成程序，用VHDL语言编写-Available is a good DDS frequency synthesis procedures, using VHDL language

adpcm .c程序代码，完整,通过编译仿真(ADPCM c program code, complete compiled simulation)