VHDL hardware design study of 100 cases (chief recommended)

实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构(Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure)

在FPGA开发板显示字符串,采用VHDL语言,以简单的功能说明FPGA的开发流程.-In the FPGA development board shows the string, using VHDL language, in a simple functional description FPGA-development process.

《Verilog HDL 程序设计教程》4-"Verilog HDL Design Guide" 4

ofdm系统的matlab实现，包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)

基于压缩感知的ISAR方位向成像以及与FFT成像对比(CS-based ISAR imaging and RD imaging)

利用AT89C51实现LCD日历电子钟源码-AT89C51 realization of the use of electronic LCD calendar clock source

用verilog实现endat2_1驱动,并用signalTap捕捉信号。(Using verilog achieve endat2_1 drive and use signalTap capture signal.)

Five day stmicroelectornics vhdl training presentation

Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model