用VHDL语言在CPLD上实现串行通信

16级流水线型cordic旋转代码以及测试文件，亲测好用(16-stage pipelined cordic rotation code and test files, pro-testing)

SMII 到 MII 转换的VHDL代码-SMII to MII conversion of VHDL code

A latch3 written in VHDL.

梁祝音乐verilog code --适用于QUATUS II 开发环境下，适合于verilog入门学员(the verilog code of liangzhu )

matlab 程序 伪随机码的捕获,我传的都是这方面的资料！(failed to translate)

说明：  通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)

利用VHDL语言设计一个分频器，输入为CLK,输出分别为CLK1、CLK8、CLK256、 CLK1024-The use of VHDL language design a divider, input CLK, the output respectively, CLK1, CLK8, CLK256, CLK1024

说明：  RISC全部源码，包含仿真文件，使用makefile脚本编写，能通过vcs编译(RISC all source code, including simulation files, using makefile script, can be compiled through VCS)

MPSK调制与解调VHDL程序源代码与仿真(MPSK modulation and demodulation process and VHDL source code and simulation)

ADC TLC5510的测试程序，经过测试通过，十分简单好用-ADC TLC5510 test procedures, after the test is very simple and easy