verilog hdl verilog hdl verilog hdl

完成cmos摄像头对图像的捕捉，然后进行拼接通过USB进行传输。(complete picture capture)

verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10

一个FIFO产生程序，主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)

early branch rename table(store rename table once the branch instruction comes in. Used in out of order pipeline processor)

无线通信FPGA设计Matlab Verilog代码(Wireless FPGA design Matlab Verilog code)

设计一个简单的FIR滤波器，并按要求确定滤波器的系统函数。(Design a simple FIR filter, and determine the filter according to the requirement of system function.)

该程序实现的是n位全加器，首先用与非门实现一位全家器，最后实现n位的全加器。-the program is to achieve the n-bit full adder, first using the door with non-realization of a family- and finally realize the full n-bit adder.

ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder

thesis about design and implementation neural network using FPGA

一个实用的uart协议模块，使用verilog 实现(A practical uart protocol modules, use verilog to achieve)