verilog hdl verilog hdl verilog hdl

vhdl经典源代码――键盘接口设计，入门者必须掌握-vhdl classical source code-- the keyboard interface design, beginners must master

基于FPGA的键盘PS第二类编码方式的verilog解码程序。基于FPGA的键盘PS第二类编码方式的verilog解码程序。(FPGA keyboard PS encoding the verilog decoding procedures. FPGA keyboard PS encoding the verilog decoding procedures.)

这是一个FIFO_Buffer的verilog代码.(This is a FIFO_Buffer the Verilog code.)

说明：  FPGA实现的AD采样控制程序的源码，欢迎大家下载(FPGA implementation of the AD sampling control)

---------------------------------------------------------------------------------- -- Company:       VISENGI S.L. (www.visengi.com) - URJC FRAV Group (www.frav.es) -- Engineer:      Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com) -- -- Create Date:    12:39:50 06-Oct-2008 -- Pr

tdma参数化模块。可以自动生成2的n次的tdma哥时隙，用户可根据需要自己配置参数(tdma see the number of model lumps. 2 n basis following manner tdma chance possible 以自 dynamic generation, for root needed self-placement see number)

说明：  通过spi实现加速度计adxl357读取xyz三轴方向的加速度值(Accelerometers adxl357 read the acceleration value of XYZ three-axis direction through SPI)

用verilog HDL语言编写的fifo存储器源文件 (Using Verilog language HDL FIFO memory source file)

自己编的一个分频器的程序模版 虽然原理很简单，经过多次实践很实用 被多次用在其它的程序中-own series of the dividers of a procedure template Although very simple principle, after repeated practice by many very practical use in other proceedings, and,

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation