verilog hdl verilog hdl verilog hdl

基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集原码 开发软件 Quartus II -ATEREAL EPM1270T144C5N CPLD-based pressure sensor data acquisition source Quartus II development software

FPGA based implementation of a SDR - codes in Verilog HDL for the processor and control.-FPGA based implementation of a SDR- codes in Verilog HDL for the processor and control.

说明：  阿尔泰PCI8664的采集卡labview程序(PCI8664，labview，programm)

本代码实现了移位寄存器功能，初学者可借鉴学习-This code implements the shift register functions, beginners can learn to learn

说明：  xilinx fpga各版本mmcm/pll动态配置RTL代码，包括testbench(xilinx fpga mmcm/pll drp RTL code, including testbench)

它是一种以地址总线数据总线为结构的8位微处理器，主要由两部分组成：一是控制单元，数据通路控制单元控制微处理器的所有块、寄存器和部件，数据通路由地址和数据通路信号处理组成指令读写加法；

其中包括AD9226的原理图和应用程序，可以参考完成其他编程(Including AD9226 schematics and applications, you can refer to complete other programming)

4*4键盘小程序 两种算法内附检查LED(4* 4 keyboard applet containing two algorithms check the LED)

说明：  altera发布的开源8b10b源代码，vhdl语言描述(altera released the source code open source 8b10b, vhdl language description)