verilog hdl verilog hdl verilog hdl

FPGA 学习实例 动态时钟、面积、速度优化相关代码(Codes related to dynamic clock, area and speed optimization for learning examples of FPGA)

QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)

分频器的VHDL程序，完整的建立工程，编译，功能功能仿真，验证-fenpinqi de vhdlchengxu gongnengfnagzhen,yanzheng

多功能卡的源代码，verilog编写，用于多功能的数据接收-verilog code of mutiple function card

Verilog 编写的IP核，512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM

说明：  本书纸版由机械工业出版社于2014年出版，张强编著，电子版由华章分社（北京华章图文信息有限公司）全球范围内制作与发行(The book was published in paperback by China machine press in 2014, and edited by zhang qiang. The electronic version was produced and distributed worldwide by huazhang branch (Beijing huazhang graphic information co., LTD.))

train controler by verilog

说明：  I2C MASTER DESIGNED by Verilog

说明：  basic verilog code on siso, piso, sipo

说明：  基于CycloneV FPGA与电阻网络的数模转换器代码，能够实现键控更改频率，通过ROM IP核存储波形数据。(Digital to analog converter code based on cyclonev FPGA and resistance network can realize keying change frequency and store waveform data through ROM IP core.)