这是“VHDL设计”讲稿，希望对初学者有用，

VHDL与源代码包-and VHDL source code

自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)

SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals in various formats. The cores connect using AXI-streams. Most configurations (resolution, framerate, colordepth, etc.) are set at compile-time using Verilog parameters. See svo_defines.vh for details on those parameters.

北京中教仪装备技术有限公司制作，关于xilinx FPGA使用的教程，包括ISE、picoblaze、microblaze等的使用说明。(some paper for the use of ise， picoblaze,microblaze)

初学ＶＨＤＬ有用的，了解后对复杂设计有很大帮助．-VHDL beginner useful understanding of the complexity of the design has been inspired by them.

huffman transform in vhdl language

说明：  there's a clock divider for DE2 altra board clock (50MHz)

基于fpga的coms摄像头 扫描，参考文献，(Fpga based on the coms camera scan, reference literature,)

Project manager is reak vhdl old man

成功解决FPGA设计时序问题的三大点.word说明文档，很详细(FPGA design timing problems successfully solved the three points)