VHDL 算术逻辑单元ALU_复旦

verilog实现的奇数分频器 针对任何规模的奇数分频-verilog prescaler for the realization of the odd-numbered odd-numbered points of any size-frequency

利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。

Ovo sto saljem je tutorijal 7 sa vhdlom

MBD-FPGA数字滤波器设计基本流程,基于DSP builder(MBD-FPGA basic process of digital filter design)

xlinx sparten 3E实验板，实现时钟闹钟功能，闹钟播放电子音乐，时钟，闹钟通过LCD屏显示。自己写的，亲测可用。                                                                                                                    

SoC sample Code using Altera Xcaliber, good usefull SoC.

FIR filter basic verilog code for implementation-FIR filter basic verilog code for implementation

开发板原理图 自己可以设计开发板为什么一定要买呢(Development board schematic can design their own development board why they must buy it)

8086微机原理实验：8251串行接口、8253计数器、数码管、跑马灯。汇编语言。(8086 microcomputer principle experiment: 8251 serial interface, the 8253 counter, digital tube, Marquee. Assembly language.)

Control with DAC conversion