坦克大战的演示程序 ，实现了基本的人机交互

实现dsp与fpga的emif的verilog异步实现，可实现异步读写以及相应功能模块控制，文件中包含仿真后的波形图形以及仿真测试程序，运行环境quartus ii11.0，仿真环境mmodelsim se 6.5d(Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d)

四位静态数码管控制器，含详细的中文注释，ＶＥＲＩＬＯＴ源码．-4 static digital tube controller, with detailed notes in Chinese, VERILOT source.

VHDL电梯控制器程序设计与仿真，内含原理图和VHDL源码，有助于学习VHFL(VHDL u7535 u68AF u63A7 u5236 u5668 u7A0B u5E8F u8BBE u8BA1 u4E0E u4EFF u771F)

里面是VHDL的一些例子，大家可以看一下，蛮不错的，对大家提高VHDL水平很好的.-There is some examples of VHDL, we can look pretty good on the U.S. improve the level VHDL good.

用VHDL开发的棒球游戏，可以在QuartusII环境下编译，适用于各种FPGA开发板。-VHDL development of the baseball game, in QuartusII environment compiler, apply to all FPGA development board.

本文设计了基于加速度传感器的计步器，并通过仿真以及实际调试得到了相应的结果的记录。本实验首先通过加速度传感器检测目标物体的运动，产生脉冲，将脉冲放大后经过施密特触发器整型为方波，并给出了方波的调试电路图。然后编写程序，利用D触发器检测方波的上升沿，当上升沿到来时，计数，并对十位、个位分别编码，然后由使能信号交替控制数码管输出结果。本文给出了仿真以及调试的程序、结果。(This article is designed pedometer-based acceleration sensor and the corresponding results recorded by simulation and debugging. The experiments by first acceleration sensor detects the movement of the target object, generates a pulse, the pulse amplification is a square wave after the Schmitt trigger integer, and gives the the debug circuit diagram of a square wave. Then write procedures, the use of the rising edge of the detection of the square wave of the D flip-flop, when the rising edge, the count, and ten bits are encoded, and then alternately by the enable signal output of the digital control. In this paper, a simulation and debugging procedures, results.)

说明：  多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)

KX_DVP3F型FPGA应用板/开发板（全套）包括：  CycloneII系列FPGA EP2C8Q208C8 40万们，含20M-270MHz锁相环2个。  RS232串行接口；VGA视频口  高速SRAM 512KB。可用于语音处理，NiosII运行等。  配置Flash EPCS2， 10万次烧写周期 。  isp单片机T89S8253：MCS51兼容单片机，12KB在系统可编程Flash ROM，10万次烧 写周期；2KB在系统可编程EEPROM，10万次烧写周期；2.7V-5.5V工作电压；0-24MHz 工作时钟；  2数码管显示器、20MHz时钟源（可通过FPGA中的锁相环倍频）；  液晶显示屏（20字X4行）；  工作电源5V、3.3V、1.2V混合电压源，良好电磁兼容性主板。  配套示例程序、资料、编程软件光盘等。  4X4键盘，4普通按键，8可锁按键，8发光管  BlasterMV编程下载器和并口通信线，可完成FPGA编程下载和isp单片机的编程。KX_DV3F开发板的源程序-err

controller for sending serial data at different speeds

含异步清零和同步清零的计数器的设计，内容是源代码，以及相关文件，打开即可(Clear cleared asynchronous and synchronous with the counter design, content source code and related documents, can be opened)