Rotary Encoder Reading the Rotary Encoder and indicating the selection through...

FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)

Firmware for autotuning Sensor

广东工业大学硕士论文《SVPWM算法优化及其FPGA/CPLD实现》，在详细分析经典SVPWM算法基础上，提出一种优化算法，并在FPGA上实现。论文附录包含VHDL源码。(Guangdong University Thesis " SVPWM algorithm to optimize its FPGA/CPLD realization" in the detailed analysis of the classical SVPWM algorithm is proposed based on an optimization algorithm, and implemented on FPGA. Paper appendix contains VHDL source code.)

说明：  环路滤波器是通信信号调制解调中最重要的一个部分，环路滤波器设计的好坏将直接影响到接收机的性能指标，二阶锁频辅助三阶锁相环路滤波器可以稳定跟踪具有加加速度的信号源，是现代通信中非常实用的技术，本文中详细编写了单载波信号产生模块、信道噪声模块、数字正交下变频模块、鉴频鉴相模块、环路滤波器模块，并包含了完整的testbench模块，对于初学者非常有用。(Loop filter is the most important part of communication signal modulation and demodulation. The design of loop filter will directly affect the performance index of receiver. The second-order frequency locking assisted third-order phase-locked loop filter can stably track the signal source with acceleration speed, which is a very practical technology in modern communication. In this paper, the single carrier signal generation module and channel noise are written in detail Sound module, digital orthogonal down conversion module, frequency and phase detection module, loop filter module, and contains a complete testbench module, which is very useful for beginners.)

通过VERILOG编写的AD9516时钟芯片SPI配置代码(CONGIGURE THE ad9516)

open cores 提供的i2c控制IP核 可直接在FPGA上使用。并带有相关的测试程序(endorsed by the i2c controller IP provided by the open cores on the FPGA. With the relevant test procedures)

这是一个计算器的Verilog代码，可实现加减乘除等基础功能(calcultor for you to do some reserches.)

fpga DDS ROM数据正弦波形正半周采样程序-fpga DDS ROM sinusoidal waveform is a half weeks of data sampling procedures

说明：  华为经典设计全套入门技巧，面试经验，设计技巧(Huawei Classic Design Complete Introduction Skills, Interview Experience, Design Skills)

基于FPGA实现IIR滤波器的程序，用VERILOG编程语言实现(The program based on the FPGA implementation of the IIR filter is implemented in the VERILOG programming language)